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1. 发明授权

US08685819B2 Method for the realization of a crossbar array of crossed conductive or semi-conductive access lines 失效
标题翻译：用于实现交叉导电或半导电接入线的交叉开关阵列的方法
公开(公告)号：US08685819B2
公开(公告)日：2014-04-01
申请号：US13154726
申请日：2011-06-07
申请人： Julien Buckley , Karim Aissou , Thierry Baron , Gabriel Molas
发明人： Julien Buckley , Karim Aissou , Thierry Baron , Gabriel Molas
IPC分类号： H01L21/8234
CPC分类号： H01L21/0331 , H01L21/0337 , H01L27/101
摘要： A method for making a crossbar array of crossed conductive or semi-conductive access lines on a substrate, the crossbar array including on a crossbar array insulator, in a plane parallel to the substrate, a first level of lines including a plurality of first lines parallel with each other made of a conductive or semi-conductive material; on the first level of lines, a second level of lines including a plurality of second lines parallel with each other made of a conductive or semi-conductive material, the second lines being substantially perpendicular to the first lines. The method includes forming, on the substrate, a first cavity of substantially rectangular shape; forming a second cavity of substantially rectangular shape superimposed to the first cavity, the first and second cavities intersecting each other perpendicularly so as to form a resultant cavity.
摘要翻译：一种用于在衬底上制造交叉导电或半导电接入线的交叉开关阵列的方法，所述交叉开关阵列包括在与所述衬底平行的平面中的交叉开关阵列绝缘体上，所述第一电平线包括多条第一线平行彼此由导电或半导体材料制成; 在第一级线上，包括由导电或半导电材料制成的彼此平行的多条第二线的第二级线，第二线基本上垂直于第一线。该方法包括在基板上形成大致矩形形状的第一空腔; 形成叠加到第一腔体上的基本矩形形状的第二腔体，第一和第二腔体垂直相交，从而形成合成腔体。

2. 发明授权

US08252702B2 Fabrication of a memory with two self-aligned independent gates 有权
标题翻译：具有两个自对准独立门的存储器的制造
公开(公告)号：US08252702B2
公开(公告)日：2012-08-28
申请号：US13091502
申请日：2011-04-21
申请人： Gabriel Molas , Thierry Baron
发明人： Gabriel Molas , Thierry Baron
IPC分类号： H01L21/31
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/42344 , H01L29/66545 , H01L29/792
摘要： A method for making a micro-electronic non-volatile memory device provided with transistors having gates placed side by side, the method comprising the steps of: a) forming in a layer based on at least one first gate material lying on a support, at least one first transistor gate block and at least one sacrificial block, said first block and said sacrificial block being separated by a given space, b) forming in said given space a stack comprising at least one insulating layer and at least one second gate material, said gate material located in said space being intended to form a second gate block separated from the first block by said insulating layer, c) suppressing said sacrificial block.
摘要翻译：一种用于制造具有并排布置的栅极的晶体管的微电子非易失性存储器件的方法，所述方法包括以下步骤：a）基于位于支撑件上的至少一个第一栅极材料，在至少一个第一晶体管栅极块和至少一个牺牲块，所述第一块和所述牺牲块由给定空间分开，b）在所述给定空间中形成包括至少一个绝缘层和至少一个第二栅极材料的堆叠，位于所述空间中的所述栅极材料旨在形成通过所述绝缘层与所述第一块分离的第二栅极块，c）抑制所述牺牲块。

3. 发明授权

US06946369B2 Method for forming, by CVD, nanostructures of semi-conductor material of homogenous and controlled size on dielectric material 有权
标题翻译：通过CVD法在电介质材料上形成均匀和受控尺寸的半导体材料的纳米结构的方法
公开(公告)号：US06946369B2
公开(公告)日：2005-09-20
申请号：US10718109
申请日：2003-11-19
申请人： Frédéric Mazen , Thierry Baron , Jean-Michel Hartmann , Marie-Noelle Semeria
发明人： Frédéric Mazen , Thierry Baron , Jean-Michel Hartmann , Marie-Noelle Semeria
IPC分类号： B82B3/00 , C23C16/04 , C30B25/00 , C30B25/02 , H01L21/20 , H01L21/205 , H01L21/28 , H01L21/285 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/788 , H01L29/792
CPC分类号： H01L29/0665 , B82Y10/00 , C23C16/04 , C30B25/00 , C30B25/02 , C30B29/605 , H01L21/0242 , H01L21/02422 , H01L21/0245 , H01L21/02513 , H01L21/02532 , H01L21/0259 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L21/28273 , H01L29/0673 , Y10S438/967
摘要： The invention concerns a method for forming nanostructures of semi-conductor material on a substrate of dielectric material by chemical vapour deposition (CVD). Said method comprises the following steps: a step of forming on the substrate (12) stable nuclei (14) of a first semi-conductor material in the form of islands, by CVD from a precursor (11) of the first semi-conductor material chosen so that the dielectric material (12) accepts the formation of said nuclei (14), a step of forming nanostructures (16A, 16B) of a second semi-conductor material from the stable nuclei (14) of the first semi-conductor material, by CVD from a precursor (21) chosen to generate a selective deposition of the second semi-conductor material only on said nuclei (14). The invention further concerns nanostructures formed according to one of said methods as well as devices comprising said nanostructures.
摘要翻译：本发明涉及通过化学气相沉积（CVD）在介电材料的衬底上形成半导体材料的纳米结构的方法。所述方法包括以下步骤：通过CVD从第一半导体材料的前体（11）在衬底（12）上形成岛状形式的第一半导体材料的稳定核（14）的步骤选择使得介电材料（12）接受所述核（14）的形成;从第一半导体材料的稳定核（14）形成第二半导体材料的纳米结构（16A，16B）的步骤，导体材料，通过CVD从前体（21）中选择以仅在所述核（14）上产生第二半导体材料的选择性沉积。本发明还涉及根据所述方法之一形成的纳米结构以及包含所述纳米结构的器件。

4. 发明授权

US06724017B2 Method for automatic organization of microstructures or nanostructures and related device obtained 有权
标题翻译：自动组织微结构或纳米结构的方法及相关装置
公开(公告)号：US06724017B2
公开(公告)日：2004-04-20
申请号：US10381212
申请日：2003-03-28
申请人： Marie-Noëlle Semeria , Pierre Mur , Franck Fournel , Hubert Moriceau , Hubert Eymery , Noël Magnea , Thierry Baron , François Martin
发明人： Marie-Noëlle Semeria , Pierre Mur , Franck Fournel , Hubert Moriceau , Hubert Eymery , Noël Magnea , Thierry Baron , François Martin
IPC分类号： H01L31109
CPC分类号： C23C16/0272 , C23C14/024 , C30B25/02 , C30B29/605
摘要： The invention relates to a device comprising microstructures or nanostructures on a support, characterized in that the support comprises: a) a substrate (1) comprising at least one part composed of a crystalline material, this part having a surface (2) with a stress field or a topology associated with a stress field, the stress field being associated with dislocations, b) an intermediate layer (3) bonded to the surface (2), and having a thickness and/or composition and/or a surface state enabling transmission of said stress field through this layer as far as its free face that supports microstructures or nanostructures (4).
摘要翻译：本发明涉及一种在载体上包含微结构或纳米结构的装置，其特征在于，所述载体包括：a）基材（1），其包含由结晶材料组成的至少一部分，该部分具有应力的表面（2）场或与应力场相关联的拓扑，所述应力场与位错相关联，b）结合到所述表面（2）的中间层（3），并且具有能够传输的厚度和/或组成和/或表面状态的所述应力场通过该层直到其支撑微结构或纳米结构的自由面（4）。

5. 发明授权

US06372536B1 II-VI semiconductor component having at least one junction between a layer containing Se and a layer containing BeTe, and process for producing the junction 失效
标题翻译： II-VI族半导体元件在含有Se的层和含有BeTe的层之间具有至少一个结，以及用于制造该结的工艺
公开(公告)号：US06372536B1
公开(公告)日：2002-04-16
申请号：US09480756
申请日：2000-01-10
申请人： Frank Fischer , Andreas Waag , Thierry Baron , Gottfried Landwehr , Thomas Litz , Günter Reuscher , Markus Keim , Ulrich Zehnder , Hans-Peter Steinbrück , Mario Nagelstrasser , Hans-Jürgen Lugauer
发明人： Frank Fischer , Andreas Waag , Thierry Baron , Gottfried Landwehr , Thomas Litz , Günter Reuscher , Markus Keim , Ulrich Zehnder , Hans-Peter Steinbrück , Mario Nagelstrasser , Hans-Jürgen Lugauer
IPC分类号： H01L2100
CPC分类号： H01L33/40 , H01L33/0087 , H01L33/28
摘要： The invention relates to a II-VI semiconductor component in which, within a series of layers, there is provided at least one junction between a semiconductor layer containing BeTe and a semiconductor layer containing Se. A boundary layer between the semiconductor layer containing BeTe and the semiconductor layer containing Se is prepared in such a way that it forms a Be—Se configuration.
摘要翻译：本发明涉及一种II-VI族半导体元件，其中在一系列层内提供了含有BeTe的半导体层和含有Se的半导体层之间的至少一个结。包含BeTe的半导体层和含有Se的半导体层之间的边界层以使其形成Be-Se构型的方式制备。

6. 发明授权

US08088674B2 Method of growing, on a dielectric material, nanowires made of semi-conductor materials connecting two electrodes 有权
标题翻译：在介电材料上生长由连接两个电极的半导体材料制成的纳米线的方法
公开(公告)号：US08088674B2
公开(公告)日：2012-01-03
申请号：US12743852
申请日：2008-11-27
申请人： Thomas Ernst , Thierry Baron , Pierre Ferret , Pascal Gentile , Bassem Salem
发明人： Thomas Ernst , Thierry Baron , Pierre Ferret , Pascal Gentile , Bassem Salem
IPC分类号： H01L21/36
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/0237 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L29/0673 , Y10S977/938
摘要： Electrodes made from metallic material are formed on a layer of dielectric material. A bottom layer of at least one of the electrodes constitutes a catalyst material in direct contact with the layer of dielectric material. Nanowires are grown by means of the catalyst, between the electrodes, parallel to the layer of dielectric material. The nanowires connecting the two electrodes are then made from single-crystal semi-conductor material and in contact with the layer of dielectric material.
摘要翻译：由金属材料制成的电极形成在电介质材料层上。至少一个电极的底层构成与电介质材料层直接接触的催化剂材料。纳米线通过催化剂在电极之间平行于介电材料层生长。连接两个电极的纳米线然后由单晶半导体材料制成并与介电材料层接触。

7. 发明申请

US20120052598A1 METHOD FOR THE REALIZATION OF A CROSSBAR ARRAY OF CROSSED CONDUCTIVE OR SEMI-CONDUCTIVE ACCESS LINES 失效
标题翻译：用于实现交叉导电或半导体访问线的十字架阵列的方法
公开(公告)号：US20120052598A1
公开(公告)日：2012-03-01
申请号：US13154726
申请日：2011-06-07
申请人： Julien Buckley , Karim Aissou , Thierry Baron , Gabriel Molas
发明人： Julien Buckley , Karim Aissou , Thierry Baron , Gabriel Molas
IPC分类号： H01L21/8246 , H01L21/02
CPC分类号： H01L21/0331 , H01L21/0337 , H01L27/101
摘要： A method for making a crossbar array of crossed conductive or semi-conductive access lines on a substrate, the crossbar array including on a crossbar array insulator, in a plane parallel to the substrate, a first level of lines including a plurality of first lines parallel with each other made of a conductive or semi-conductive material; on the first level of lines, a second level of lines including a plurality of second lines parallel with each other made of a conductive or semi-conductive material, the second lines being substantially perpendicular to the first lines. The method includes forming, on the substrate, a first cavity of substantially rectangular shape; forming a second cavity of substantially rectangular shape superimposed to the first cavity, the first and second cavities intersecting each other perpendicularly so as to form a resultant cavity.
摘要翻译：一种用于在衬底上制造交叉导电或半导电接入线的交叉开关阵列的方法，所述交叉开关阵列包括在与所述衬底平行的平面中的交叉开关阵列绝缘体上，所述第一电平线包括多条第一线平行彼此由导电或半导体材料制成; 在第一级线上，包括由导电或半导电材料制成的彼此平行的多条第二线的第二级线，第二线基本上垂直于第一线。该方法包括在基板上形成大致矩形形状的第一空腔; 形成叠加到第一腔体上的基本矩形形状的第二腔体，第一和第二腔体垂直相交，从而形成合成腔体。

8. 发明授权

US07968398B2 Method for producing a floating gate with an alternation of lines of first and second materials 有权
标题翻译：用于制造具有第一和第二材料的线的交替的浮动栅极的方法
公开(公告)号：US07968398B2
公开(公告)日：2011-06-28
申请号：US12320269
申请日：2009-01-22
申请人： Gabriel Molas , Karim Aissou , Thierry Baron
发明人： Gabriel Molas , Karim Aissou , Thierry Baron
IPC分类号： H01L21/8238
CPC分类号： H01L29/42332 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/7881 , H01L29/792
摘要： A diblock copolymer layer comprising at least two polymers and having a lamellar structure perpendicularly to a substrate is deposited on a first gate insulator formed on the substrate. One of the polymers of the diblock copolymer layer is then eliminated to form parallel grooves in the copolymer layer. The grooves are filled by a first metallic or semi-conductor material and the rest of the copolymer layer is eliminated. A second dielectric material is deposited to form a second gate insulator. The second gate insulator of the floating gate then comprises an alternation of parallel first and second lines respectively of the first and second materials, the second material encapsulating the lines of the first material.
摘要翻译：包含至少两种聚合物并且具有垂直于衬底的层状结构的二嵌段共聚物层沉积在形成在衬底上的第一栅极绝缘体上。然后消除二嵌段共聚物层的聚合物之一，以在共聚物层中形成平行的沟槽。凹槽由第一金属或半导体材料填充，而其余的共聚物层被去除。沉积第二介电材料以形成第二栅极绝缘体。浮栅的第二栅极绝缘体然后分别包括第一和第二材料的平行的第一和第二线的交替，第二材料封装第一材料的线。

9. 发明申请

US20100273317A1 METHOD OF GROWING, ON A DIELETRIC MATERIAL, NANOWIRES MADE OF SEMI-CONDUCTOR MATERIALS CONNECTING TWO ELECTRODES 有权
标题翻译：在非线性材料上生长的方法，连接两个电极的半导体材料的纳米管
公开(公告)号：US20100273317A1
公开(公告)日：2010-10-28
申请号：US12743852
申请日：2008-11-27
申请人： Thomas Ernst , Thierry Baron , Pierre Ferret , Pascal Gentile , Bassem Salem
发明人： Thomas Ernst , Thierry Baron , Pierre Ferret , Pascal Gentile , Bassem Salem
IPC分类号： H01L21/20
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/0237 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L29/0673 , Y10S977/938
摘要： Electrodes made from metallic material are formed on a layer of dielectric material. A bottom layer of at least one of the electrodes constitutes a catalyst material in direct contact with the layer of dielectric material. Nanowires are grown by means of the catalyst, between the electrodes, parallel to the layer of dielectric material. The nanowires connecting the two electrodes are then made from single-crystal semi-conductor material and in contact with the layer of dielectric material.
摘要翻译：由金属材料制成的电极形成在电介质材料层上。至少一个电极的底层构成与电介质材料层直接接触的催化剂材料。纳米线通过催化剂在电极之间平行于介电材料层生长。连接两个电极的纳米线然后由单晶半导体材料制成并与介电材料层接触。

10. 发明申请

US20090203205A1 Method for producing a floating gate with an alternation of lines of first and second materials 有权
标题翻译：用于制造具有第一和第二材料的线的交替的浮动栅极的方法
公开(公告)号：US20090203205A1
公开(公告)日：2009-08-13
申请号：US12320269
申请日：2009-01-22
申请人： Gabriel Molas , Karim Aissou , Thierry Baron
发明人： Gabriel Molas , Karim Aissou , Thierry Baron
IPC分类号： H01L21/28
CPC分类号： H01L29/42332 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/7881 , H01L29/792
摘要： A diblock copolymer layer comprising at least two polymers and having a lamellar structure perpendicularly to a substrate is deposited on a first gate insulator formed on the substrate. One of the polymers of the diblock copolymer layer is then eliminated to form parallel grooves in the copolymer layer. The grooves are filled by a first metallic or semi-conductor material and the rest of the copolymer layer is eliminated. A second dielectric material is deposited to form a second gate insulator. The second gate insulator of the floating gate then comprises an alternation of parallel first and second lines respectively of the first and second materials, the second material encapsulating the lines of the first material.
摘要翻译：包含至少两种聚合物并且具有垂直于衬底的层状结构的二嵌段共聚物层沉积在形成在衬底上的第一栅极绝缘体上。然后消除二嵌段共聚物层的聚合物之一，以在共聚物层中形成平行的沟槽。凹槽由第一金属或半导体材料填充，而其余的共聚物层被去除。沉积第二介电材料以形成第二栅极绝缘体。浮栅的第二栅极绝缘体然后分别包括第一和第二材料的平行的第一和第二线的交替，第二材料封装第一材料的线。

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