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1. 发明申请

US20070041248A1 Semiconductor storage device and method of manufacturing the same 有权
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US20070041248A1
公开(公告)日：2007-02-22
申请号：US11498817
申请日：2006-08-04
申请人： Tetsuji Togami
发明人： Tetsuji Togami
IPC分类号： G11C11/34 , H01L29/00 , H01L23/58 , H01L23/62 , H01L29/94
CPC分类号： G11C8/08 , H01L27/112 , H01L27/11253
摘要： A method of manufacturing a semiconductor storage device according to an embodiment of the present invention includes forming dummy cells 611, to 618 at a position adjacent to a reference cell 412, and implanting an impurity into the dummy cells 611, to 618 using a mask that covers the reference cell 412. Here, the process of implanting the impurity is carried out so that the impurity exudes out of the dummy cells 611, to 618 to the reference cell 412.
摘要翻译：根据本发明的实施例的制造半导体存储装置的方法包括在与参考单元41相邻的位置处形成虚设单元61 1至61 8，并使用覆盖参考单元41的掩模将杂质注入到虚拟单元61 1〜61中，以达到61×8 < / SUB>。这里，进行注入杂质的处理，使得杂质从空电池61 1〜61中分散到参考电池41 2的61 <8> 。

2. 发明授权

US07859905B2 Semiconductor storage device and method of manufacturing the same 有权
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US07859905B2
公开(公告)日：2010-12-28
申请号：US11498817
申请日：2006-08-04
申请人： Tetsuji Togami
发明人： Tetsuji Togami
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , H01L27/112 , H01L27/11253
摘要： A method of manufacturing a semiconductor storage device according to an embodiment of the present invention includes forming dummy cells 611, to 618 at a position adjacent to a reference cell 412, and implanting an impurity into the dummy cells 611, to 618 using a mask that covers the reference cell 412. Here, the process of implanting the impurity is carried out so that the impurity exudes out of the dummy cells 611, to 618 to the reference cell 412.
摘要翻译：根据本发明的实施例的制造半导体存储装置的方法包括在与参考单元412相邻的位置处形成虚设单元611至618，并将杂质注入到虚设单元611中，使用掩模覆盖参考单元412.这里，执行注入杂质的处理，使得杂质从虚设单元611中散出到618到参考单元412。

3. 发明授权

US06479874B2 Semiconductor memory device having multilevel memory cell and method of manufacturing the same 失效
标题翻译：具有多层存储单元的半导体存储器件及其制造方法
公开(公告)号：US06479874B2
公开(公告)日：2002-11-12
申请号：US09161510
申请日：1998-09-28
申请人： Kenji Hibino , Masao Kunitou , Kazuyuki Yamasaki , Tetsuji Togami , Hironori Sakamoto , Kiyokazu Hashimoto
发明人： Kenji Hibino , Masao Kunitou , Kazuyuki Yamasaki , Tetsuji Togami , Hironori Sakamoto , Kiyokazu Hashimoto
IPC分类号： H01L2976
CPC分类号： H01L27/112 , G11C11/5692 , H01L27/11253
摘要： A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.
摘要翻译：一种半导体ROM器件，其能够获得可以安全地区分存储在存储单元中的数据的参考电流，所述多级屏蔽ROM用于存储每个存储单元的三级或更多级的多级数据。该装置包括存储单元，其中相应于注入到单元晶体管的沟道区域的离子的量设置阈值电压，并存储三个或多个电平的多电平数据，用于产生用于比较的参考电流的参考单元从存储器单元读出电流，以及与参考单元相邻设置的虚拟单元。在参考单元的沟道区域和虚拟单元的沟道区域中，同时注入离子以在参考单元和虚拟单元中建立相等的阈值电压。

4. 发明授权

US06204541B1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06204541B1
公开(公告)日：2001-03-20
申请号：US09559141
申请日：2000-04-27
申请人： Tetsuji Togami , Kazuteru Suzuki
发明人： Tetsuji Togami , Kazuteru Suzuki
IPC分类号： H01L2711
CPC分类号： G11C8/12 , G11C16/0491 , G11C17/126 , H01L27/115
摘要： In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line diffused interconnections 2 connected to one virtual ground line terminal VG1 through bank selection transistors BT3 to BT6 are connected to sources of memory cells of the four column pairs. The bank selection transistors BT1 to BT6 are so located that each of the bit line diffused interconnections 1 is connected to a corresponding one of the bit line terminals D0 and D1 through only one bank selection transistor and each of bit line diffused interconnections 2 is connected to the virtual ground line terminal VG1 through only one bank selection transistor. Thus, data can be surely read from a selected memory cell at a high speed. At the time of elevating the integrated density, it is easy to locate and pattern metal interconnections connected to the bit line terminal and the virtual ground line terminal.
摘要翻译：在半导体存储器中，通过存储体选择晶体管BT1和BT2连接到两个位线端子D0和D1的四位线扩散互连1分别连接到四列对的存储单元的漏极，四个位线扩散互连2连接到通过存储体选择晶体管BT3至BT6的一个虚拟接地线端子VG1连接到四列对的存储单元的源极。存储体选择晶体管BT1至BT6的位置使得位线扩散互连1中的每一个仅通过一个存储体选择晶体管连接到位线端子D0和D1中的相应一个，并且每个位线扩散互连2连接到虚拟接地线端子VG1只通过一个选择晶体管。因此，可以以高速可靠地从所选存储单元读取数据。在提高集成密度时，容易定位和图案连接到位线端子和虚拟接地线端子的金属互连。

5. 发明授权

US6037815A Pulse generating circuit having address transition detecting circuit 失效
标题翻译：具有地址转换检测电路的脉冲发生电路
公开(公告)号：US6037815A
公开(公告)日：2000-03-14
申请号：US859102
申请日：1997-05-20
申请人： Tetsuji Togami
发明人： Tetsuji Togami
IPC分类号： G11C11/41 , G11C8/18 , G11C11/407 , G11C11/409 , H03K5/1534 , H03K3/017
CPC分类号： H03K5/1534 , G11C8/18
摘要： A pulse generating circuit which has a first and a second delay circuit selectively operable as a delay circuit or a resetting circuit. The delay circuits each has a discharge transistor and a charge transistor in order to fix the potential on its associated node rapidly when operating as a resetting circuit. Even when short pulses are continuously input as an input signal by accident, the circuitry surely outputs a single pulse transitioning at the same time as the first change in the input signal and having a desired duration since the last change in the input signal.
摘要翻译：一种脉冲发生电路，其具有选择性地用作延迟电路或复位电路的第一和第二延迟电路。延迟电路各自具有放电晶体管和充电晶体管，以便当作为复位电路工作时，将电位迅速固定在其相关联的节点上。即使短时脉冲作为输入信号被意外地连续地输入，电路确实输出与输入信号中的第一次变化同时的单个脉冲转换，并且具有自输入信号的最后一次变化以来的期望持续时间。

6. 发明授权

US06269028B1 Method and apparatus for multistage readout operation 失效
标题翻译：多级读出操作的方法和装置
公开(公告)号：US06269028B1
公开(公告)日：2001-07-31
申请号：US09661631
申请日：2000-09-13
申请人： Tetsuji Togami
发明人： Tetsuji Togami
IPC分类号： G11C700
CPC分类号： G11C7/106 , G11C7/1048 , G11C7/1051 , G11C11/5621 , G11C11/5642 , G11C2211/5642
摘要： According to one embodiment, a multistage readout circuit may include a smaller circuit size and/or faster circuit response. A memory cell (002) may have more than two states (VT0-VT3). Determination of a particular state can involve various stage results generated by activating a word line at different levels. A sense amplifier (003) can provide an output value at each stage. In one arrangement, a second stage value can determine if a memory cell (002) has two of four states and can be latched in a first latch circuit (041). Such a second stage value can then determine if a first stage value or third stage value is latched in a second latch circuit (042). A first/third value can determine if a memory cell (002) has one of the two states initially determined by the second stage value.
摘要翻译：根据一个实施例，多级读出电路可以包括较小的电路尺寸和/或更快的电路响应。存储单元（002）可以具有多于两种状态（VT0-VT3）。确定特定状态可以涉及通过激活不同级别的字线而产生的各种阶段结果。读出放大器（003）可以在每个阶段提供一个输出值。在一种布置中，第二级值可以确定存储器单元（002）是否具有四种状态中的两种，并且可以锁存在第一锁存电路（041）中。这样的第二级值就可以确定第一级值或第三级值是否被锁存在第二锁存电路（042）中。第一/第三值可以确定存储器单元（002）是否具有由第二级值初始确定的两种状态之一。

7. 发明授权

US6081474A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US6081474A
公开(公告)日：2000-06-27
申请号：US156615
申请日：1998-09-18
申请人： Tetsuji Togami , Kazuteru Suzuki
发明人： Tetsuji Togami , Kazuteru Suzuki
IPC分类号： G11C16/06 , G11C8/12 , G11C16/04 , G11C17/12 , G11C17/18 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , G11C8/00
CPC分类号： G11C8/12 , G11C16/0491 , G11C17/126 , H01L27/115
摘要： In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line diffused interconnections 2 connected to one virtual ground line terminal VG1 through bank selection transistors BT3 to BT6 are connected to sources of memory cells of the four column pairs. The bank selection transistors BT1 to BT6 are so located that each of the bit line diffused interconnections 1 is connected to a corresponding one of the bit line terminals D0 and D1 through only one bank selection transistor and each of bit line diffused interconnections 2 is connected to the virtual ground line terminal VG1 through only one bank selection transistor. Thus, data can be surely read from a selected memory cell at a high speed. At the time of elevating the integrated density, it is easy to locate and pattern metal interconnections connected to the bit line terminal and the virtual ground line terminal.
摘要翻译：在半导体存储器中，通过存储体选择晶体管BT1和BT2连接到两个位线端子D0和D1的四位线扩散互连1分别连接到四列对的存储单元的漏极，四个位线扩散互连2连接到通过存储体选择晶体管BT3至BT6的一个虚拟接地线端子VG1连接到四列对的存储单元的源极。存储体选择晶体管BT1至BT6的位置使得位线扩散互连1中的每一个仅通过一个存储体选择晶体管连接到位线端子D0和D1中的相应一个，并且每个位线扩散互连2连接到虚拟接地线端子VG1只通过一个选择晶体管。因此，可以以高速可靠地从所选存储单元读取数据。在提高集成密度时，容易定位和图案连接到位线端子和虚拟接地线端子的金属互连。

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