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1. 发明授权

US06596600B1 Integrated injection logic semiconductor device and method of fabricating the same 有权
标题翻译：集成注入逻辑半导体器件及其制造方法
公开(公告)号：US06596600B1
公开(公告)日：2003-07-22
申请号：US09182520
申请日：1998-10-30
申请人： Takayuki Gomi
发明人： Takayuki Gomi
IPC分类号： H01L218228
CPC分类号： H01L27/0233
摘要： A logic circuit is formed of an I2L cell structure in which a difference of switching speeds at every collectors in a multi-collector structure is small. In a semiconductor device in which an integrated injection logic cell including a constant current source transistor and a switch transistor is formed on a common semiconductor substrate, a first semiconductor layer (13) doped with a first conductivity type impurity and a second semiconductor layer (19) doped with a second conductivity impurity are electrically isolated from each other on a semiconductor substrate. A plurality of collector electrodes of the switch transistor and a plurality of collector regions (20) based on diffusion of impurity are formed by the second semiconductor layer (19). The first semiconductor layer (13) includes a base electrode deriving portion, and a direct contact portion which directly contacts with the semiconductor substrate between a plurality of collector regions (20). An external base region (17) is formed by diffusion of first conductivity type impurity from the direct contact portion.
摘要翻译：逻辑电路由I2L单元结构形成，其中多集电极结构中的每个集电极的开关速度差异小。在公共半导体衬底上形成有包括恒流源晶体管和开关晶体管的集成注入逻辑单元的半导体器件中，掺杂有第一导电型杂质的第一半导体层（13）和第二半导体层（19 ）掺杂有第二导电杂质在半导体衬底上彼此电隔离。由第二半导体层（19）形成开关晶体管的多个集电极和基于杂质扩散的多个集电极区域（20）。第一半导体层（13）包括基极导出部分和在多个集电极区域（20）之间与半导体衬底直接接触的直接接触部分。通过从直接接触部分扩散第一导电型杂质形成外部基极区（17）。

2. 发明授权

US5912479A Heterojunction bipolar semiconductor device 失效
标题翻译：异质结双极半导体器件
公开(公告)号：US5912479A
公开(公告)日：1999-06-15
申请号：US900698
申请日：1997-07-25
申请人： Hideki Mori , Takayuki Gomi
发明人： Hideki Mori , Takayuki Gomi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/337 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L29/732 , H01L29/737 , H01L29/80 , H01L29/808 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L27/0623 , H01L21/8248 , H01L29/7378 , H01L29/802
摘要： A semiconductor device includes a heterojunction bipolar transistor and a junction gate type field effect transistor which are formed on a semiconductor base. A base region and graft base regions of the heterojunction bipolar transistor, and a channel region and source/drain regions of the junction gate type field effect transistor, are formed of a first semiconductor layer of a first conduction type. The first semiconductor layer is formed of mixed crystals of silicon-germanium which has a higher carrier mobility than silicon. An emitter region of the heterojunction bipolar transistor and a gate region of the junction gate type field effect transistor are formed of a second semiconductor layer of a second conduction type which makes a heterojunction with the first semiconductor layer.
摘要翻译：半导体器件包括形成在半导体基底上的异质结双极晶体管和结栅型场效应晶体管。异质结双极晶体管的基极区域和接枝基极区域以及结栅型场效应晶体管的沟道区域和源极/漏极区域由第一导电类型的第一半导体层形成。第一半导体层由具有比硅更高的载流子迁移率的硅 - 锗混合晶体形成。异质结双极晶体管的发射极区域和结栅型场效应晶体管的栅极区域由与第一半导体层形成异质结的第二导电类型的第二半导体层形成。

3. 发明授权

US5830799A Method for forming embedded diffusion layers using an alignment mark 失效
标题翻译：使用对准标记形成嵌入扩散层的方法
公开(公告)号：US5830799A
公开(公告)日：1998-11-03
申请号：US700081
申请日：1996-08-20
申请人： Hiroaki Ammo , Shigeru Kanematsu , Takayuki Gomi
发明人： Hiroaki Ammo , Shigeru Kanematsu , Takayuki Gomi
IPC分类号： H01L29/73 , H01L21/265 , H01L21/331 , H01L21/74 , H01L21/8228 , H01L23/544 , H01L27/082 , H01L29/732 , H01L27/06
CPC分类号： H01L21/26513 , H01L21/74 , H01L21/8228 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975
摘要： To form NPN and PNP transistors on the same base for example to obtain a complementary bipolar transistor it has been necessary to make an epitaxial layer a thick film, and this has resulted in deterioration of the characteristics of the NPN transistor. Also, because a step of forming an alignment mark has been necessary this has increased the number of manufacturing steps needed to make a complementary bipolar transistor. This invention provides a semiconductor device manufacturing method which solves this problem as follows: After a first opening 13 (alignment mark 16) and a second opening 14 are formed in an insulating film 12 formed on a semiconductor base 11 and a doping mask 15 is then formed on the semiconductor base 11, a third opening 17 is formed thereon with the alignment mark 16 as a reference. After an impurity 18 is introduced into the semiconductor base 11 through the third opening 17, the doping mask 15 is removed and after that an impurity 19 is introduced into the semiconductor base 11 by solid-phase diffusion through the second opening 14 and a first embedded diffusion layer 20 is thereby formed and at the same time the impurity 18 is caused to diffuse and form a second embedded diffusion layer 21. Then, after an epitaxial layer is formed, an impurity diffusion layer is formed therein by ion injection (not shown).
摘要翻译：为了在相同的基底上形成NPN和PNP晶体管以获得互补双极晶体管，必须使外延层成为厚膜，这导致NPN晶体管的特性劣化。此外，由于需要形成对准标记的步骤，这增加了制造互补双极晶体管所需的制造步骤的数量。本发明提供如下解决该问题的半导体器件制造方法：在形成在半导体基底11上的绝缘膜12和掺杂掩模15中形成第一开口13（对准标记16）和第二开口14之后形成在半导体基板11上的第三开口17上形成有对准标记16作为基准。在通过第三开口17将杂质18引入半导体基底11之后，去除掺杂掩模15，然后通过固相扩散通过第二开口14将杂质19引入半导体基底11中，并且第一嵌入从而形成扩散层20，同时使杂质18扩散并形成第二嵌入扩散层21.然后，在形成外延层之后，通过离子注入（未示出）在其中形成杂质扩散层，。

4. 发明授权

US5786258A Method of making an SOI transistor 失效
公开(公告)号：US5786258A
公开(公告)日：1998-07-28
申请号：US786879
申请日：1997-01-23
申请人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
发明人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
IPC分类号： H01L29/73 , H01L21/22 , H01L21/331 , H01L21/38
CPC分类号： H01L29/7317 , H01L29/66265
摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

5. 发明授权

US5622887A Process for fabricating BiCMOS devices including passive devices 失效
标题翻译：用于制造BiCMOS器件的工艺，包括无源器件
公开(公告)号：US5622887A
公开(公告)日：1997-04-22
申请号：US323873
申请日：1994-10-17
申请人： Hiroyuki Miwa , Mamoru Shinohara , Takayuki Gomi , Tomotaka Fujisawa
发明人： Hiroyuki Miwa , Mamoru Shinohara , Takayuki Gomi , Tomotaka Fujisawa
IPC分类号： H01L27/06 , H01L21/70
CPC分类号： H01L27/0623
摘要： A semiconductor device comprising a MIS structure comprising a first electrically conductive film formed on an oxide film, a second electrically conductive film formed on at least a part of said first electrically conductive film, an insulator film formed on said second electrically conductive film, and a third electrically conductive film formed on said insulator film; and at least one electrode contact portion formed on said first electrically conductive film. A semiconductor device comprising a MIS capacitor having a diffusion layer inside the semiconductor substrate as a lower electrode with a first electrically conductive type being isolated using another diffusion layer having the opposite conductive type, and said another diffusion layer having the opposite conductive type being further isolated using a diffusion layer for isolation having the first conductive type and which is earthed. A BiCMOS semiconductor device comprising a resistor and an impurity source for the emitter and the emitter electrode for the bipolar transistor made of a same conductor layer, and further, a same conductor layer is provided as the contact electrode for the resistor and the gate for the MOS transistor. Also claimed are processes for fabricating the aforementioned semiconductor devices.
摘要翻译：一种包括MIS结构的半导体器件，包括形成在氧化膜上的第一导电膜，形成在所述第一导电膜的至少一部分上的第二导电膜，形成在所述第二导电膜上的绝缘膜，形成在所述绝缘膜上的第三导电膜; 以及形成在所述第一导电膜上的至少一个电极接触部分。一种半导体器件，包括具有扩散层的MIS电容器，该半导体衬底内的扩散层作为具有第一导电类型的下电极，使用具有相反导电类型的另一扩散层来隔离，并且所述另一个具有相反导电类型的扩散层进一步隔离使用具有第一导电类型并且接地的用于隔离的扩散层。一种BiCMOS半导体器件，包括电阻器和用于由相同导体层制成的双极晶体管的发射极和发射极的杂质源，并且还提供相同的导体层作为电阻器的接触电极和用于 MOS晶体管还要求保护的是制造上述半导体器件的工艺。

6. 发明授权

US5580797A Method of making SOI Transistor 失效
标题翻译：制造SOI晶体管的方法
公开(公告)号：US5580797A
公开(公告)日：1996-12-03
申请号：US245767
申请日：1994-05-18
申请人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
发明人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
IPC分类号： H01L29/73 , H01L21/22 , H01L21/331 , H01L21/38 , H01L21/265
CPC分类号： H01L29/7317 , H01L29/66265
摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.
摘要翻译：公开了能够形成窄尺寸扩散区域（例如基底宽度）的横向双极晶体管。晶体管在扩散区域的宽度方向上没有散射。通过在半导体部分中以大致均匀的浓度改变杂质扩散源并通过从杂质扩散源扩散形成扩散区来减小发射极电阻。双极晶体管具有SOI结构。还公开了制造这种装置的方法。

7. 发明授权

US4994881A Bipolar transistor 失效
标题翻译：双极晶体管
公开(公告)号：US4994881A
公开(公告)日：1991-02-19
申请号：US309235
申请日：1989-02-13
申请人： Takayuki Gomi
发明人： Takayuki Gomi
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/36 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/0826 , H01L29/36
摘要： An improved bipolar transistor is a vertical type bipolar transistor the base region of which is composed of a graft base region, an intrinsic base region separated from the graft base region and having an emitter region in its inside, and a link impurity diffusion region linking these regions. In the preparation, the graft base region is formed by diffusion of impurities from the base contact electrode layer and the emitter region formed in the intrinsic base region may be formed in self-alignment. In the vicinity of the junction between the base region and the semiconductor substrate, there is formed a diffusion suppression region composed of an impurity diffusion region of a conductivity type opposite to the conductivity type of the base region and adapted for preventing the depth of junction from being increased.

8. 发明授权

US4844312A Apparatus for controlling traverse position of running strip 失效
标题翻译：用于控制运行条的横移位置的装置
公开(公告)号：US4844312A
公开(公告)日：1989-07-04
申请号：US149117
申请日：1988-01-27
申请人： Takayuki Gomi , Fumio Kitamura
发明人： Takayuki Gomi , Fumio Kitamura
IPC分类号： B65H23/038 , H01F41/02
CPC分类号： B65H23/038 , H01F41/0213
摘要： In an apparatus for controlling a traverse direction of a running strip, a deviation of the running strip in the traverse direction with respect to a reference position is calculated, and the running strip is moved in the transverse direction in accordance with the deviation, thereby correcting the traverse position of the running strip.

9. 发明申请

US20140042530A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140042530A1
公开(公告)日：2014-02-13
申请号：US13963161
申请日：2013-08-09
申请人： Min-Kwon CHO , Takayuki GOMI , Chan-Ho PARK , Nam-Ki CHO , Won-Sang CHOI
发明人： Min-Kwon CHO , Takayuki GOMI , Chan-Ho PARK , Nam-Ki CHO , Won-Sang CHOI
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/41766 , H01L29/456 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/78 , H01L29/7811 , H01L29/7813 , H01L29/7827
摘要： A semiconductor device includes a substrate including a first region and a second region, a trench-gate transistor in the first region, the trench-gate transistor including a first trench in the substrate, a gate filling at least part of the first trench, and a source in the substrate and on each sidewall of the first trench, a first field diffusion junction in the second region, an interlayer insulating film on the substrate, the interlayer insulating film covering the trench-gate transistor and the first field diffusion junction, a first contact in the first region, the first contact passing through the interlayer insulating film and contacting the source, and a second contact in the second region, the second contact passing through the interlayer insulating film and contacting the first field diffusion junction, the first contact and the second contact having an equal height and including a same material.
摘要翻译：一种半导体器件包括：包括第一区域和第二区域的衬底;第一区域中的沟槽栅极晶体管，沟槽栅极晶体管包括衬底中的第一沟槽，填充至少部分第一沟槽的栅极，以及在第一沟槽的衬底和每个侧壁上的源极，第二区域中的第一场扩散结，衬底上的层间绝缘膜，覆盖沟槽栅晶体管的层间绝缘膜和第一场扩散结，所述第一接触通过所述层间绝缘膜并接触所述源，所述第二接触在所述第二区域中，所述第二接触通过所述层间绝缘膜并接触所述第一场扩散结，所述第一接触并且第二触点具有相同的高度并且包括相同的材料。

10. 发明授权

US5893743A Process of fabricating semiconductor device 失效
标题翻译：制造半导体器件的工艺
公开(公告)号：US5893743A
公开(公告)日：1999-04-13
申请号：US877422
申请日：1997-06-17
申请人： Takayuki Gomi , Hiroaki Ammo
发明人： Takayuki Gomi , Hiroaki Ammo
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/732
CPC分类号： H01L21/82285
摘要： A process for forming a first bipolar transistor having a single polysilicon structure and a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor on the same substrate. In the process of fabricating a semiconductor device in which a first bipolar transistor having a single polysilicon structure, a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor, and a third bipolar transistor having a double polysilicon structure are provided on the same semiconductor substrate, a base contact portion of the first bipolar transistor and an emitter of the second bipolar transistor are formed in the same step, and an emitter of the first bipolar transistor and base contact portions of the second and third bipolar transistors are formed in the same step.
摘要翻译：一种用于形成具有单个多晶硅结构的第一双极晶体管和具有单个多晶硅结构并且在同一衬底上具有与第一双极晶体管相反的导电类型的第二双极晶体管的工艺。在制造其中具有单个多晶硅结构的第一双极晶体管，具有单个多晶硅结构并且具有与第一双极晶体管相反的导电类型的第二双极晶体管的半导体器件的过程中，以及第三双极晶体管，在相同的半导体衬底上设置双重多晶硅结构，第一双极晶体管的基极接触部分和第二双极晶体管的发射极在同一步骤中形成，并且第一双极晶体管和基极接触部分的发射极在同一步骤中形成第二和第三双极晶体管。

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