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1. 发明授权

US08354728B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08354728B2
公开(公告)日：2013-01-15
申请号：US12836826
申请日：2010-07-15
申请人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
发明人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
IPC分类号： H01L29/76 , H01L29/94 , H01L29/788 , H01L27/148 , H01L29/768
CPC分类号： H01L29/7834 , H01L23/5225 , H01L23/585 , H01L29/0638 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/402 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
摘要翻译：一种半导体器件，包括：半导体层; 栅极绝缘层; 栅电极; 一个通道区域源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层，其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层，其中当从所述顶侧观察时，所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中，所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上，所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域在从顶侧观察的通道宽度方向上。

2. 发明申请

US20080237747A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080237747A1
公开(公告)日：2008-10-02
申请号：US12129191
申请日：2008-05-29
申请人： Masahiro HAYASHI , Takahisa AKIBA , Kunio WATANABE , Tomo TAKASO , Susumu KENMOCHI
发明人： Masahiro HAYASHI , Takahisa AKIBA , Kunio WATANABE , Tomo TAKASO , Susumu KENMOCHI
IPC分类号： H01L29/00
CPC分类号： H01L29/7834 , H01L23/5225 , H01L23/585 , H01L29/0638 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/402 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
摘要翻译：一种半导体器件，包括：半导体层; 栅极绝缘层; 栅电极; 一个通道区; 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层，其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层，其中当从所述顶侧观察时，所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中，所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上，所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域在从顶侧观察的通道宽度方向上。

3. 发明申请

US20070096250A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070096250A1
公开(公告)日：2007-05-03
申请号：US11529635
申请日：2006-09-28
申请人： Kunio Watanabe , Tomo Takaso , Masahiro Hayashi , Takahisa Akiba , Susumu Kenmochi
发明人： Kunio Watanabe , Tomo Takaso , Masahiro Hayashi , Takahisa Akiba , Susumu Kenmochi
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L23/5258 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a transistor formed in the semiconductor layer; a first interlayer dielectric formed above the semiconductor layer; a plurality of first interconnect layers formed above the first interlayer dielectric; a second interlayer dielectric formed over the first interlayer dielectric and the first interconnect layers; a plurality of second interconnect layers and an electrode pad which are formed above the second interlayer dielectric, the second interconnect layers being uppermost interconnects; a passivation layer formed over the second interlayer dielectric, the second interconnect layers, and the electrode pad; and an opening formed in the passivation layer to expose at least part of the electrode pad, a minimum distance between the second interconnect layers being greater than a minimum distance between the first interconnect layers.
摘要翻译：一种半导体器件，包括：半导体层; 形成在半导体层中的晶体管; 形成在所述半导体层上方的第一层间电介质; 形成在所述第一层间电介质上方的多个第一互连层; 形成在所述第一层间电介质和所述第一互连层上的第二层间电介质; 多个第二互连层和电极焊盘，形成在第二层间电介质的上方，第二互连层是最上面的互连; 形成在所述第二层间电介质上的钝化层，所述第二互连层和所述电极焊盘; 以及形成在所述钝化层中以暴露所述电极焊盘的至少一部分的开口，所述第二互连层之间的最小距离大于所述第一互连层之间的最小距离。

4. 发明申请

US20060270182A1 MANUFACTURING PROCESS OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件和半导体器件的制造工艺
公开(公告)号：US20060270182A1
公开(公告)日：2006-11-30
申请号：US11382183
申请日：2006-05-08
申请人： Takahisa AKIBA , Taishi FUKIDA
发明人： Takahisa AKIBA , Taishi FUKIDA
IPC分类号： H01L29/76 , H01L21/76
CPC分类号： H01L21/76235 , H01L29/6659 , H01L29/7833
摘要： A manufacturing process of a semiconductor device, includes: forming a ground oxide film, which includes over a well region of a first conductive type, on a silicon semiconductor substrate; forming a nitride film over the ground oxide film; forming a mask pattern by selectively etching the nitride film and the ground oxide film; forming a trench by etching the semiconductor substrate according to the mask pattern; wet etching to retreat an edge part of the ground oxide film; oxidizing a surface inside the trench through a dry oxidation atmosphere at a temperature of 1,030 to 1,070° C.; annealing at a temperature higher than the oxidation; embedding an insulating film inside the trench; leveling out the insulating film; removing the mask pattern; removing a remaining film of the ground oxide film; forming a pre-oxide film on the semiconductor substrate; forming on the first conductive type region an impurity region of a second conductive type with a depth crossing the insulating film; etching to eliminate the pre-oxide film, and, at the same time, to make a round shape surface of an upper part of the trench exposed; forming a gate insulating film on the first conductive type region such that the edge part side may be placed from over the edge part of the impurity region of the second conductive type to over the edge part of the insulating film; and forming a gate electrode on the gate insulating film.
摘要翻译：半导体器件的制造工艺包括：在硅半导体衬底上形成包括在第一导电类型的阱区域上的研磨氧化物膜; 在所述研磨的氧化膜上形成氮化物膜; 通过选择性地蚀刻氮化物膜和研磨的氧化物膜来形成掩模图案; 通过根据掩模图案蚀刻半导体衬底来形成沟槽; 湿法蚀刻以使后部的磨碎氧化膜的边缘部分退回; 在1,030至1,070℃的温度下通过干燥氧化气氛氧化沟槽内的表面; 在高于氧化温度下进行退火; 在沟槽内嵌入绝缘膜; 平整绝缘膜; 去除掩模图案; 去除残留的研磨氧化膜的膜; 在半导体衬底上形成预氧化膜; 在第一导电类型区域上形成具有与绝缘膜交叉的深度的第二导电类型的杂质区域; 蚀刻以消除预氧化物膜，同时，使沟槽上部的圆形表面露出; 在所述第一导电类型区域上形成栅极绝缘膜，使得所述边缘部分侧可以从所述第二导电类型的杂质区域的边缘部分的上方放置到所述绝缘膜的边缘部分上方; 以及在所述栅极绝缘膜上形成栅电极。

5. 发明授权

US07906821B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07906821B2
公开(公告)日：2011-03-15
申请号：US12129191
申请日：2008-05-29
申请人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
发明人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
IPC分类号： H01L29/76 , H01L29/94 , H01L29/788 , H01L27/148 , H01L29/768
CPC分类号： H01L29/7834 , H01L23/5225 , H01L23/585 , H01L29/0638 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/402 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
摘要翻译：一种半导体器件，包括：半导体层; 栅极绝缘层; 栅电极; 一个通道区; 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层，其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层，其中当从所述顶侧观察时，所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中，所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上，所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域在从顶侧观察的通道宽度方向上。

6. 发明授权

US07394137B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07394137B2
公开(公告)日：2008-07-01
申请号：US11519169
申请日：2006-09-11
申请人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
发明人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7834 , H01L23/5225 , H01L23/585 , H01L29/0638 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/402 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
摘要翻译：一种半导体器件，包括：半导体层; 栅极绝缘层; 栅电极; 一个通道区; 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层，其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层，其中当从所述顶侧观察时，所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中，所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上，所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域在从顶侧观察的通道宽度方向上。

7. 发明申请

US20050139869A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050139869A1
公开(公告)日：2005-06-30
申请号：US11022068
申请日：2004-12-23
申请人： Takahisa Akiba , Masahiko Tsuyuki , Kenji Yokoyama
发明人： Takahisa Akiba , Masahiko Tsuyuki , Kenji Yokoyama
IPC分类号： H01L21/76 , H01L21/336 , H01L27/148 , H01L29/06 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66568 , H01L29/0649 , H01L29/1033
摘要： A semiconductor device is provided including a gate insulation layer formed on a semiconductor substrate, a source and drain region, an offset region composed of a doped layer of which concentration is low comparing to that of the source region and drain region and surrounds the source region and drain region, and a channel stopper region formed on the outside of the offset region. The channel stopper region includes a protrusion toward the long side direction of the gate insulation layer such that the distance between the gate insulation layer and the channel stopper region is narrower than the distance between the offset region and the channel stopper region.
摘要翻译：提供一种半导体器件，包括形成在半导体衬底上的栅极绝缘层，源极和漏极区域，与源极区域和漏极区域相比浓度低的掺杂层构成的偏移区域，并且包围源极区域漏极区域和形成在偏移区域的外侧上的沟道阻挡区域。通道停止区域包括朝向栅极绝缘层的长边方向的突起，使得栅极绝缘层和沟道阻挡区域之间的距离比偏移区域和沟道阻挡区域之间的距离窄。

8. 发明申请

US20100276762A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100276762A1
公开(公告)日：2010-11-04
申请号：US12836826
申请日：2010-07-15
申请人： Masahiro HAYASHI , Takahisa AKIBA , Kunio WATANABE , Tomo TAKASO , Susumu KENMOCHI
发明人： Masahiro HAYASHI , Takahisa AKIBA , Kunio WATANABE , Tomo TAKASO , Susumu KENMOCHI
IPC分类号： H01L29/78
CPC分类号： H01L29/7834 , H01L23/5225 , H01L23/585 , H01L29/0638 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/402 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
摘要翻译：一种半导体器件，包括：半导体层; 栅极绝缘层; 栅电极; 一个通道区域源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层，其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层，其中当从所述顶侧观察时，所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中，所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上，所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域在从顶侧观察的通道宽度方向上。

9. 发明申请

US20060286733A1 Method for manufacturing a semiconductor element 有权
公开(公告)号：US20060286733A1
公开(公告)日：2006-12-21
申请号：US11453638
申请日：2006-06-14
申请人： Masahiro Hayashi , Takahisa Akiba , Akihiro Shiraishi
发明人： Masahiro Hayashi , Takahisa Akiba , Akihiro Shiraishi
IPC分类号： H01L21/8234
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823857
摘要： A method for manufacturing a semiconductor element, comprises: (1) forming a first insulating layer for electric field relaxation that is thicker than a first gate insulating layer in a first channel region of a transistor of a first conductive type that is one of P-type and N-type polarity formed on a semiconductor silicon wafer to surround an edge of a first gate electrode in order to reduce an electric field concentrated to a region surrounding the edge of the first gate electrode because of a voltage applied to the first gate electrode and a first drain region of the transistor of the first conductive type, and forming a second insulating layer for electric field relaxation that is thicker than a second gate insulating layer in a second channel region of a transistor of a second conductive type to surround the edge of the first gate electrode in order to reduce an electric field concentrated to a region surrounding an edge of a second gate electrode because of a voltage applied to the second gate electrode and a second drain region of the transistor of the second conductive type; (2) forming a first photoresist layer in an uppermost section of the wafer; (3) forming a first resist pattern by performing first photolithography to remove the photoresist layer in a region where ion implantation of an impurity of the first conductive type is to be performed for forming a first region for electric field relaxation so as to surround the drain region of the transistor of the first conductive type and the first insulating layer for electric field relaxation; (4) removing the first resist pattern after the ion implantation of the impurity of the first conductive type by employing the first resist pattern as a mask; (5) performing first heat treatment to diffuse the impurity of the first conductive type; (6) forming a second photoresist layer in an uppermost section of the wafer; (7) forming a second resist pattern by performing second photolithography to remove the second photoresist layer in a region where ion implantation of an impurity of the second conductive type is to be performed for forming a second region for electric field relaxation so as to surround the drain region of the transistor of the second conductive type and the second insulating layer for electric field relaxation; (8) removing the second resist pattern after the ion implantation of the impurity of the second conductive type by employing the second resist pattern as a mask; and (9) performing second heat treatment to form the first region for electric field relaxation and the second region for electric field relaxation. The first region for electric field relaxation is provided by the first heat treatment to diffuse the impurity of the first conductive type in (5) and the second heat treatment in (9).

10. 发明申请

US20070096246A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070096246A1
公开(公告)日：2007-05-03
申请号：US11583095
申请日：2006-10-18
申请人： Takahisa Akiba , Kunio Watanabe , Masahiro Hayashi , Tomo Takaso , Susumu Kenmochi
发明人： Takahisa Akiba , Kunio Watanabe , Masahiro Hayashi , Tomo Takaso , Susumu Kenmochi
IPC分类号： H01L29/06 , H01L23/58
CPC分类号： H01L29/0653 , H01L29/7834
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer formed above the semiconductor layer; a gate electrode formed above the gate insulating layer; a channel region formed in the semiconductor layer; a source region and a drain region formed in the semiconductor layer; and an offset insulating layer formed in the semiconductor layer and at least between the channel region and the source region and between the channel region and the drain region, a ratio of a length in a depth direction and a length in a channel length direction of the offset insulating layer being one or less.
摘要翻译：一种半导体器件，包括：半导体层; 形成在半导体层上方的栅极绝缘层; 形成在所述栅绝缘层上的栅电极; 形成在所述半导体层中的沟道区; 形成在所述半导体层中的源极区域和漏极区域; 以及偏移绝缘层，形成在所述半导体层中，并且至少在所述沟道区域和所述源极区域之间以及所述沟道区域和所述漏极区域之间，所述沟道区域和所述漏极区域之间的深度方向上的长度和沟道长度方向上的长度的比率偏移绝缘层为1个以下。

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