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1. 发明授权

US08354728B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08354728B2
公开(公告)日：2013-01-15
申请号：US12836826
申请日：2010-07-15
申请人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
发明人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
IPC分类号： H01L29/76 , H01L29/94 , H01L29/788 , H01L27/148 , H01L29/768
CPC分类号： H01L29/7834 , H01L23/5225 , H01L23/585 , H01L29/0638 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/402 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
摘要翻译：一种半导体器件，包括：半导体层; 栅极绝缘层; 栅电极; 一个通道区域源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层，其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层，其中当从所述顶侧观察时，所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中，所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上，所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域在从顶侧观察的通道宽度方向上。

2. 发明申请

US20070096250A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070096250A1
公开(公告)日：2007-05-03
申请号：US11529635
申请日：2006-09-28
申请人： Kunio Watanabe , Tomo Takaso , Masahiro Hayashi , Takahisa Akiba , Susumu Kenmochi
发明人： Kunio Watanabe , Tomo Takaso , Masahiro Hayashi , Takahisa Akiba , Susumu Kenmochi
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L23/5258 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a transistor formed in the semiconductor layer; a first interlayer dielectric formed above the semiconductor layer; a plurality of first interconnect layers formed above the first interlayer dielectric; a second interlayer dielectric formed over the first interlayer dielectric and the first interconnect layers; a plurality of second interconnect layers and an electrode pad which are formed above the second interlayer dielectric, the second interconnect layers being uppermost interconnects; a passivation layer formed over the second interlayer dielectric, the second interconnect layers, and the electrode pad; and an opening formed in the passivation layer to expose at least part of the electrode pad, a minimum distance between the second interconnect layers being greater than a minimum distance between the first interconnect layers.
摘要翻译：一种半导体器件，包括：半导体层; 形成在半导体层中的晶体管; 形成在所述半导体层上方的第一层间电介质; 形成在所述第一层间电介质上方的多个第一互连层; 形成在所述第一层间电介质和所述第一互连层上的第二层间电介质; 多个第二互连层和电极焊盘，形成在第二层间电介质的上方，第二互连层是最上面的互连; 形成在所述第二层间电介质上的钝化层，所述第二互连层和所述电极焊盘; 以及形成在所述钝化层中以暴露所述电极焊盘的至少一部分的开口，所述第二互连层之间的最小距离大于所述第一互连层之间的最小距离。

3. 发明申请

US20070096246A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070096246A1
公开(公告)日：2007-05-03
申请号：US11583095
申请日：2006-10-18
申请人： Takahisa Akiba , Kunio Watanabe , Masahiro Hayashi , Tomo Takaso , Susumu Kenmochi
发明人： Takahisa Akiba , Kunio Watanabe , Masahiro Hayashi , Tomo Takaso , Susumu Kenmochi
IPC分类号： H01L29/06 , H01L23/58
CPC分类号： H01L29/0653 , H01L29/7834
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer formed above the semiconductor layer; a gate electrode formed above the gate insulating layer; a channel region formed in the semiconductor layer; a source region and a drain region formed in the semiconductor layer; and an offset insulating layer formed in the semiconductor layer and at least between the channel region and the source region and between the channel region and the drain region, a ratio of a length in a depth direction and a length in a channel length direction of the offset insulating layer being one or less.
摘要翻译：一种半导体器件，包括：半导体层; 形成在半导体层上方的栅极绝缘层; 形成在所述栅绝缘层上的栅电极; 形成在所述半导体层中的沟道区; 形成在所述半导体层中的源极区域和漏极区域; 以及偏移绝缘层，形成在所述半导体层中，并且至少在所述沟道区域和所述源极区域之间以及所述沟道区域和所述漏极区域之间，所述沟道区域和所述漏极区域之间的深度方向上的长度和沟道长度方向上的长度的比率偏移绝缘层为1个以下。

4. 发明申请

US20070057280A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070057280A1
公开(公告)日：2007-03-15
申请号：US11519169
申请日：2006-09-11
申请人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
发明人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
IPC分类号： H01L29/74
CPC分类号： H01L29/7834 , H01L23/5225 , H01L23/585 , H01L29/0638 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/402 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
摘要翻译：一种半导体器件，包括：半导体层; 栅极绝缘层; 栅电极; 一个通道区; 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层，其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层，其中当从所述顶侧观察时，所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中，所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上，所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域在从顶侧观察的通道宽度方向上。

5. 发明授权

US07906821B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07906821B2
公开(公告)日：2011-03-15
申请号：US12129191
申请日：2008-05-29
申请人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
发明人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
IPC分类号： H01L29/76 , H01L29/94 , H01L29/788 , H01L27/148 , H01L29/768
CPC分类号： H01L29/7834 , H01L23/5225 , H01L23/585 , H01L29/0638 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/402 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
摘要翻译：一种半导体器件，包括：半导体层; 栅极绝缘层; 栅电极; 一个通道区; 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层，其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层，其中当从所述顶侧观察时，所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中，所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上，所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域在从顶侧观察的通道宽度方向上。

6. 发明授权

US07394137B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07394137B2
公开(公告)日：2008-07-01
申请号：US11519169
申请日：2006-09-11
申请人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
发明人： Masahiro Hayashi , Takahisa Akiba , Kunio Watanabe , Tomo Takaso , Susumu Kenmochi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7834 , H01L23/5225 , H01L23/585 , H01L29/0638 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/402 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
摘要翻译：一种半导体器件，包括：半导体层; 栅极绝缘层; 栅电极; 一个通道区; 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层，其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层，其中当从所述顶侧观察时，所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中，所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上，所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域在从顶侧观察的通道宽度方向上。

7. 发明申请

US20070057314A1 Integrated circuit device and electronic instrument 审中-公开
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070057314A1
公开(公告)日：2007-03-15
申请号：US11515909
申请日：2006-09-06
申请人： Kanji Natori , Kimihiro Maemura , Tomo Takaso , Kunio Watanabe , Masahiro Hayashi
发明人： Kanji Natori , Kimihiro Maemura , Tomo Takaso , Kunio Watanabe , Masahiro Hayashi
IPC分类号： H01L29/788
CPC分类号： G11C16/0416 , G09G3/3688 , G09G3/3696 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A programmable ROM block provided in an integrated circuit device includes a memory cell having a single-layer-gate structure in which a floating gate used in common as gates of a write/read transistor and an erase transistor is opposite to a control gate formed of an impurity layer through an insulating layer. The memory cell the cell was backward has a triple-well structure including a shallow well of a first conductivity type formed on a deep well of a second conductivity type, a ring-shaped shallow well of the second conductivity type which encloses the shallow well of the first conductivity type, and top impurity regions formed in the shallow well of the first conductivity type and the ring-shaped shallow well of the second conductivity type.
摘要翻译：设置在集成电路器件中的可编程ROM块包括具有单层栅极结构的存储单元，其中，作为写入/读取晶体管和擦除晶体管的栅极共同使用的浮动栅极与由控制栅极形成的控制栅极相反通过绝缘层的杂质层。电池后退的存储单元具有三阱结构，其包括形成在第二导电类型的深阱上的第一导电类型的浅阱，第二导电类型的环状浅阱，其包围浅阱第一导电类型和形成在第一导电类型的浅阱中的顶部杂质区域和第二导电类型的环形浅阱。

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