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1. 发明申请

WO2009022304A2 SECURE STORAGE OF A CODEWORD WITHIN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：安全存储一个集成电路内的代码
公开(公告)号：WO2009022304A2
公开(公告)日：2009-02-19
申请号：PCT/IB2008/053253
申请日：2008-08-13
申请人： NXP B.V. , PELGROM, Marcel , VERTREGT, Maarten , TUINHOUT, Hans, Paul
发明人： PELGROM, Marcel , VERTREGT, Maarten , TUINHOUT, Hans, Paul
IPC分类号： G11C17/12
CPC分类号： G11C7/24 , G11C11/41
摘要： The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (μA, μB, μC) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the value of the codeword from the integrated circuit (10), and a method for altering the value of the codeword.
摘要翻译：本发明公开了一种用于安全地存储码字的集成电路（10）。码字的值取决于集成电路的至少一个晶体管（TRA，TRB，TRC）的迁移率（μA，μB，μC）。本发明还公开了一种读取器装置（15），一种用于确定来自集成电路（10）的码字的值的方法，以及一种用于改变码字的值的方法。

2. 发明申请

WO2006114747A3 FET DEVICE 审中-公开
标题翻译： FET器件
公开(公告)号：WO2006114747A3
公开(公告)日：2007-04-05
申请号：PCT/IB2006051249
申请日：2006-04-21
申请人： KONINKL PHILIPS ELECTRONICS NV , TUINHOUT HANS P
发明人： TUINHOUT HANS P
IPC分类号： H01L29/10 , H01L27/02 , H01L27/088 , H01L29/423
CPC分类号： H01L29/4238 , H01L29/1033
摘要： The invention provides a FET device (1) with a channel region (2) with a trapezoidal shape in which the linear drain edge (7) is larger than the linear source edge (8). In this way the equality or matching of the DC parameters of two or more FET devices (1) may be improved with respect to rectangular shaped FET devices (100) while simultaneously maintaining a comparable current capability. Alternatively, the total device area of the FET device (1) may be reduced with respect to the rectangular shaped FET device (100), thereby reducing the capacitive loading while maintaining a similar equality or matching of the DC parameters of two or more FET devices (1).
摘要翻译：本发明提供了具有梯形形状的沟道区域（2）的FET器件（1），其中线性漏极边缘（7）大于线性源极边缘（8）。以这种方式，可以相对于矩形FET器件（100）改善两个或多个FET器件（1）的DC参数的相等或匹配，同时保持可比的电流能力。或者，可以相对于矩形FET器件（100）减小FET器件（1）的总器件面积，从而降低电容负载，同时保持两个或更多个FET器件的DC参数的类似等同或匹配（1）。

3. 发明申请

WO2006114747A2 FET DEVICE 审中-公开
标题翻译： FET器件
公开(公告)号：WO2006114747A2
公开(公告)日：2006-11-02
申请号：PCT/IB2006/051249
申请日：2006-04-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TUINHOUT, Hans, P.
发明人： TUINHOUT, Hans, P.
CPC分类号： H01L29/4238 , H01L29/1033
摘要： The invention provides a FET device (1) with a channel region (2) with a trapezoidal shape in which the linear drain edge (7) is larger than the linear source edge (8). In this way the equality or matching of the DC parameters of two or more FET devices (1) may be improved with respect to rectangular shaped FET devices (100) while simultaneously maintaining a comparable current capability. Alternatively, the total device area of the FET device (1) may be reduced with respect to the rectangular shaped FET device (100), thereby reducing the capacitive loading while maintaining a similar equality or matching of the DC parameters of two or more FET devices (1).
摘要翻译：本发明提供了具有梯形形状的沟道区域（2）的FET器件（1），其中线性漏极边缘（7）大于线性源极边缘（8）。以这种方式，可以相对于矩形FET器件（100）改善两个或多个FET器件（1）的DC参数的相等或匹配，同时保持可比的电流能力。或者，可以相对于矩形FET器件（100）减小FET器件（1）的总器件面积，从而降低电容负载，同时保持两个或更多个FET器件的DC参数的类似等同或匹配（1）。

4. 发明申请

WO2009022304A3 SECURE STORAGE OF A CODEWORD WITHIN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路中安全存储编码
公开(公告)号：WO2009022304A3
公开(公告)日：2009-04-09
申请号：PCT/IB2008053253
申请日：2008-08-13
申请人： NXP BV , PELGROM MARCEL , VERTREGT MAARTEN , TUINHOUT HANS PAUL
发明人： PELGROM MARCEL , VERTREGT MAARTEN , TUINHOUT HANS PAUL
IPC分类号： G11C17/12 , G06K19/073 , G11C7/20
CPC分类号： G11C7/24 , G11C11/41
摘要： The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (µA, µB, µC) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the value of the codeword from the integrated circuit (10), and a method for altering the value of the codeword.
摘要翻译：本发明公开了一种用于安全地存储码字的集成电路（10）。码字的值取决于集成电路的至少一个晶体管（TRA，TRB，TRC）的迁移率（μA，μB，μC）。本发明还公开了一种读取器装置（15），一种用于从集成电路（10）确定码字的值的方法，以及用于改变码字值的方法。

5. 发明申请

WO03105229A2 RESISTOR NETWORK SUCH AS A RESISTOR LADDER NETWORK AND A METHOD FOR MANUFACTURING SUCH A RESISTOR NETWORK 审中-公开
标题翻译：作为电阻器网络的电阻网络和用于制造这种电阻网络的方法
公开(公告)号：WO03105229A2
公开(公告)日：2003-12-18
申请号：PCT/IB0302192
申请日：2003-05-21
申请人： KONINKL PHILIPS ELECTRONICS NV , TUINHOUT HANS P , HOOGZAAD GIAN , VERTREGT MAARTEN
发明人： TUINHOUT HANS P , HOOGZAAD GIAN , VERTREGT MAARTEN
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08 , H03M1/06
CPC分类号： H01L27/0802
摘要： The invention relates to a resistor network (2) such as a resistor ladder network, comprising at least a resistor body (4) which is provided with at least a column (6) of taps (8) situated between a first tap and a second tap, wherein, in use, at least two taps can be connected with respective first and second sources of reference input potentials, and wherein each tap of the at least one column of taps can be used for outputting an output potential via a contact area which is connected with the concerning tap, wherein the resistor body (4) comprises a multiple of resistor sub-bodies (5), wherein each resistor sub-body (5) is connected with a column (6) of taps (8), and wherein the only electrical connections between the resistor sub-bodies (5) are established by electrical connections via taps (8) connected with the resistor sub-bodies (5). Furthermore the invention relates to a method for manufacturing a resistor network (2) such as a resistor ladder network.
摘要翻译：本发明涉及一种电阻网络（2），例如电阻梯形网络，至少包括一个电阻体（4），该电阻器体（4）至少设置有位于第一抽头和第二抽头之间的抽头（6）的至少一列抽头，其中在使用中，至少两个抽头可以与相应的第一和第二参考输入电位源连接，并且其中所述至少一列抽头的每个抽头可以用于经由接触区域输出输出电位，所述接触区域与所述有关抽头连接，其中所述电阻体（4）包括多个电阻子体（5），其中每个电阻子体（5）与抽头（8）的列（6）连接，以及其中通过与电阻子体（5）连接的抽头（8）的电连接来建立电阻子体（5）之间的唯一电连接。此外，本发明涉及一种用于制造诸如电阻梯形网络的电阻网络（2）的方法。

6. 发明申请

WO2012119900A1 MAGNETIC SENSORS 审中-公开
标题翻译：磁传感器
公开(公告)号：WO2012119900A1
公开(公告)日：2012-09-13
申请号：PCT/EP2012/053419
申请日：2012-02-29
申请人： NXP B.V. , ZIEREN, Victor , VAN VELDHOVEN, Robert , WUNNICKE, Olaf , TUINHOUT, Hans
发明人： ZIEREN, Victor , VAN VELDHOVEN, Robert , WUNNICKE, Olaf , TUINHOUT, Hans
IPC分类号： G01R33/06 , H01L29/82 , G01R33/00
CPC分类号： G01R35/005 , G01R33/0035 , G01R33/06 , G01R33/066 , H01L29/82
摘要： The disclosure relates to the field of magnetic sensors, sensor governing circuits and associated methods. Certain disclosed embodiments relate to semiconductor (e.g. silicon-based) magnetic sensors, including a magnetic sensor assembly comprising a semiconductor layer (17), the semiconductor layer comprising a first collector (113) and a second collector (114), a first emitter (111) and a second emitter (112); and a governing circuit (120) configured to control and measure current flow independently between the first collector and first emitter in a first direction, and between the second collector and second emitter in a second opposing direction.
摘要翻译：本公开涉及磁传感器，传感器控制电路和相关方法领域。某些公开的实施例涉及半导体（例如基于硅的）磁传感器，包括包括半导体层（17）的磁传感器组件，该半导体层包括第一集电极（113）和第二集电极（114），第一发射极 111）和第二发射器（112）; 以及配置成在第一方向上在第一集电器和第一发射极之间以及在第二相对方向上在第二集电极和第二发射极之间独立地控制和测量电流的控制电路（120）。

7. 发明申请

WO2008015603A1 DEVICE AND METHOD FOR GENERATING A RANDOM BIT STRING 审中-公开
标题翻译：用于产生随机位字符串的装置和方法
公开(公告)号：WO2008015603A1
公开(公告)日：2008-02-07
申请号：PCT/IB2007/052821
申请日：2007-07-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SKORIC, Boris , TUYLS, Pim, T. , SALTERS, Roelof, H., W. , TUINHOUT, Hans, P. , AKKERMANS, Antonius, H., M.
发明人： SKORIC, Boris , TUYLS, Pim, T. , SALTERS, Roelof, H., W. , TUINHOUT, Hans, P. , AKKERMANS, Antonius, H., M.
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H04L9/0866
摘要： The invention relates to generating a bit string based on the circumstances of a breakdown of a diode or a number of diodes (11, 21, 31, 41, 51). One or more diodes (11, 21, 31, 41, 51) are fed with a voltage exceeding a breakdown voltage of the diodes (11, 21, 31, 41, 51) connected to a diode breakdown processor (13, 23, 33, 43, 53), which detects the breakdown and optionally relevant circumstances such as an exact breakdown voltage, and generates a bit string based on the detection, which may be used as a unique identifier or as a secret key.
摘要翻译：本发明涉及基于二极管或多个二极管（11,21,31,41,51）的击穿情况来产生位串。一个或多个二极管（11,21,31,41,51）被馈送超过连接到二极管击穿处理器（13,23,33）的二极管（11,21,31,41,51）的击穿电压的电压，43,53），其检测故障和可选的相关情况，例如精确击穿电压，并且基于检测生成可以用作唯一标识符或秘密密钥的位串。

8. 发明申请

WO2003105229A3 RESISTOR NETWORK SUCH AS A RESISTOR LADDER NETWORK AND A METHOD FOR MANUFACTURING SUCH A RESISTOR NETWORK 审中-公开
公开(公告)号：WO2003105229A3
公开(公告)日：2003-12-18
申请号：PCT/IB2003/002192
申请日：2003-05-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TUINHOUT, Hans, P. , HOOGZAAD, Gian , VERTREGT, Maarten
发明人： TUINHOUT, Hans, P. , HOOGZAAD, Gian , VERTREGT, Maarten
IPC分类号： H01L27/08
摘要： The invention relates to a resistor network (2) such as a resistor ladder network, comprising at least a resistor body (4) which is provided with at least a column (6) of taps (8) situated between a first tap and a second tap, wherein, in use, at least two taps can be connected with respective first and second sources of reference input potentials, and wherein each tap of the at least one column of taps can be used for outputting an output potential via a contact area which is connected with the concerning tap, wherein the resistor body (4) comprises a multiple of resistor sub-bodies (5), wherein each resistor sub-body (5) is connected with a column (6) of taps (8), and wherein the only electrical connections between the resistor sub-bodies (5) are established by electrical connections via taps (8) connected with the resistor sub-bodies (5). Furthermore the invention relates to a method for manufacturing a resistor network (2) such as a resistor ladder network.

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