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1. 发明申请

WO2009022304A3 SECURE STORAGE OF A CODEWORD WITHIN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路中安全存储编码
公开(公告)号：WO2009022304A3
公开(公告)日：2009-04-09
申请号：PCT/IB2008053253
申请日：2008-08-13
申请人： NXP BV , PELGROM MARCEL , VERTREGT MAARTEN , TUINHOUT HANS PAUL
发明人： PELGROM MARCEL , VERTREGT MAARTEN , TUINHOUT HANS PAUL
IPC分类号： G11C17/12 , G06K19/073 , G11C7/20
CPC分类号： G11C7/24 , G11C11/41
摘要： The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (µA, µB, µC) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the value of the codeword from the integrated circuit (10), and a method for altering the value of the codeword.
摘要翻译：本发明公开了一种用于安全地存储码字的集成电路（10）。码字的值取决于集成电路的至少一个晶体管（TRA，TRB，TRC）的迁移率（μA，μB，μC）。本发明还公开了一种读取器装置（15），一种用于从集成电路（10）确定码字的值的方法，以及用于改变码字值的方法。

2. 发明申请

WO2009034518A3 TIME-INTERLEAVED TRACK AND HOLD 审中-公开
标题翻译：时间间隔跟踪和保持
公开(公告)号：WO2009034518A3
公开(公告)日：2009-05-22
申请号：PCT/IB2008053628
申请日：2008-09-09
申请人： NXP BV , LOUWSMA SIMON MINZE , VERTREGT MAARTEN
发明人： LOUWSMA SIMON MINZE , VERTREGT MAARTEN
IPC分类号： G11C27/02
CPC分类号： H03K19/018528 , G11C27/026
摘要： The present application relates to an apparatus comprising a first transistor element, with at least three terminals, and at least one switching unit. The present application relates also to a method, computer readable medium having a computer program stored thereon and a track and hold circuit comprising the apparatus. The apparatus comprises a first transistor element with at least three terminals, wherein a first terminal is supplied with a first voltage, and wherein a second terminal is supplied with a second voltage. The apparatus comprises a first switching unit, wherein a third terminal is connected to ground potential via the first switching unit. The transistor element comprises a predefined threshold voltage. The first voltage and the second voltage are predefined alternating voltages. The transistor element is configured such that in case a differential voltage between the first predefined alternating voltage and the second predefined alternating voltage is higher than the predefined threshold voltage and the first switching unit is not conductive the third terminal is charged with the first predefined alternating voltage.
摘要翻译：本申请涉及一种包括具有至少三个端子的第一晶体管元件和至少一个开关单元的装置。本申请还涉及一种其上存储有计算机程序的计算机可读介质和包括该装置的跟踪和保持电路的方法。该装置包括具有至少三个端子的第一晶体管元件，其中第一端子被提供有第一电压，并且其中第二端子被提供有第二电压。该装置包括第一开关单元，其中第三端子经由第一开关单元连接到地电位。晶体管元件包括预定义的阈值电压。第一电压和第二电压是预定的交流电压。晶体管元件被配置为使得在第一预定交流电压和第二预定交流电压之间的差分电压高于预定阈值电压并且第一开关单元不导通的情况下，第三端子被充电第一预定交流电压。

3. 发明申请

WO2008149259A2 CIRCUIT WITH A SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER 审中-公开
标题翻译：具有连续逼近模拟数字转换器的电路
公开(公告)号：WO2008149259A2
公开(公告)日：2008-12-11
申请号：PCT/IB2008052080
申请日：2008-05-27
申请人： NXP BV , LOUWSMA SIMON M , VERTREGT MAARTEN
发明人： LOUWSMA SIMON M , VERTREGT MAARTEN
IPC分类号： H03M1/46
CPC分类号： H03M1/462 , H03M1/144
摘要： During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and compared to the analog input signal. The digital reference values are selected dependent on comparison results. In the selection of the digital reference values successive steps between digital reference values are each selected dependent on values of the comparator result from a plurality of preceding recursion cycles. The comparison results define a series of successively narrower ranges of digital values that contain a digital representation of the analog input signal. Use of a plurality of comparator results for selecting the steps in the digital reference values makes it possible to reduce uncertainty about whether the comparison result has settled. This in turn makes it possible to reduce the sizes of the successive ranges, which speeds up convergence.
摘要翻译：在逐次近似模拟到数字转换期间，选择一系列连续的数字参考值，其朝向模拟输入信号的数字表示收敛。根据连续的数字参考值产生模拟参考信号，并与模拟输入信号进行比较。根据比较结果选择数字参考值。在数字参考值的选择中，数字参考值之间的连续步骤分别根据多个先前递归周期的比较器结果的值来选择。比较结果定义了包含模拟输入信号的数字表示的一系列连续较窄的数字值范围。使用多个比较器结果来选择数字参考值中的步骤使得可以减小比较结果是否已经确定的不确定性。这又可以减小连续范围的尺寸，这加快了收敛速度。

4. 发明申请

WO2007116325A2 SECURITY STORAGE OF ELECTRONIC KEYS WITHIN VOLATILE MEMORIES 审中-公开
标题翻译：电子存储在易失性存储器中的安全存储
公开(公告)号：WO2007116325A2
公开(公告)日：2007-10-18
申请号：PCT/IB2007050495
申请日：2007-02-15
申请人： NXP BV , TUYLS PIM , VERTREGT MAARTEN , DE JONG HANS , LIST FRANS , WAGNER MATHIAS , ZACHARIASSE FRANK , MELS ARJAN
发明人： TUYLS PIM , VERTREGT MAARTEN , DE JONG HANS , LIST FRANS , WAGNER MATHIAS , ZACHARIASSE FRANK , MELS ARJAN
IPC分类号： G06F21/55
CPC分类号： G06F21/556 , H04L9/0877
摘要： It is described a method for providing an electronic key within an integrated circuit (100) including both a volatile memory (102) and a non-volatile memory (104). The described comprises starting up the integrated circuit (100), reading the logical state of predetermined data storage cells (102a) assigned to the volatile memory (102), which data storage cells (102a) are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and generating an electronic key by using the logical state of the predetermined data storage cells (102a). Preferably, the predetermined data storage cells (102a) are randomly distributed within the volatile memory (102). It is further described an integrated circuit (100) for providing an electronic key. The integrated circuit (100) comprises a volatile memory (102) comprising predetermined data storage cells (102a), which are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and a non-volatile memory (104) having information stored upon regarding the predetermined data storage cells (102a). Thereby, the electronic key is defined by the corresponding logical states of the predetermined data storage cells (102a).
摘要翻译：描述了在包括易失性存储器（102）和非易失性存储器（104）的集成电路（100）内提供电子钥匙的方法。所描述的包括启动集成电路（100），读取分配给易失性存储器（102）的预定数据存储单元（102a）的逻辑状态，哪个数据存储单元（102a）的特征在于具有多个启动过程它们分别采用相同的逻辑状态，并且通过使用预定数据存储单元（1022）的逻辑状态来生成电子密钥。优选地，预定数据存储单元（102a）被随机分布在易失性存储器（102）内。进一步描述了用于提供电子钥匙的集成电路（100）。集成电路（100）包括包括预定数据存储单元（102）的易失性存储器（102），其特征在于，通过多个启动过程，它们分别采用相同的逻辑状态，以及非易失性存储器（104）具有关于预定数据存储单元（102a）存储的信息。由此，电子密钥由预定数据存储单元（102a）的相应逻辑状态定义。

5. 发明申请

WO03105229A2 RESISTOR NETWORK SUCH AS A RESISTOR LADDER NETWORK AND A METHOD FOR MANUFACTURING SUCH A RESISTOR NETWORK 审中-公开
标题翻译：作为电阻器网络的电阻网络和用于制造这种电阻网络的方法
公开(公告)号：WO03105229A2
公开(公告)日：2003-12-18
申请号：PCT/IB0302192
申请日：2003-05-21
申请人： KONINKL PHILIPS ELECTRONICS NV , TUINHOUT HANS P , HOOGZAAD GIAN , VERTREGT MAARTEN
发明人： TUINHOUT HANS P , HOOGZAAD GIAN , VERTREGT MAARTEN
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08 , H03M1/06
CPC分类号： H01L27/0802
摘要： The invention relates to a resistor network (2) such as a resistor ladder network, comprising at least a resistor body (4) which is provided with at least a column (6) of taps (8) situated between a first tap and a second tap, wherein, in use, at least two taps can be connected with respective first and second sources of reference input potentials, and wherein each tap of the at least one column of taps can be used for outputting an output potential via a contact area which is connected with the concerning tap, wherein the resistor body (4) comprises a multiple of resistor sub-bodies (5), wherein each resistor sub-body (5) is connected with a column (6) of taps (8), and wherein the only electrical connections between the resistor sub-bodies (5) are established by electrical connections via taps (8) connected with the resistor sub-bodies (5). Furthermore the invention relates to a method for manufacturing a resistor network (2) such as a resistor ladder network.
摘要翻译：本发明涉及一种电阻网络（2），例如电阻梯形网络，至少包括一个电阻体（4），该电阻器体（4）至少设置有位于第一抽头和第二抽头之间的抽头（6）的至少一列抽头，其中在使用中，至少两个抽头可以与相应的第一和第二参考输入电位源连接，并且其中所述至少一列抽头的每个抽头可以用于经由接触区域输出输出电位，所述接触区域与所述有关抽头连接，其中所述电阻体（4）包括多个电阻子体（5），其中每个电阻子体（5）与抽头（8）的列（6）连接，以及其中通过与电阻子体（5）连接的抽头（8）的电连接来建立电阻子体（5）之间的唯一电连接。此外，本发明涉及一种用于制造诸如电阻梯形网络的电阻网络（2）的方法。

6. 发明专利

AT523964T 未知
公开(公告)号：AT523964T
公开(公告)日：2011-09-15
申请号：AT08763122
申请日：2008-05-27
申请人： NXP BV
发明人： LOUWSMA SIMON , VERTREGT MAARTEN
IPC分类号： H03M1/46

7. 发明专利

DE602007008546D1 SICHERHEITSSPEICHERUNG ELEKTRONISCHER SCHLÜSSEL INNERHALB FLÜCHTIGER SPEICHER 未知
公开(公告)号：DE602007008546D1
公开(公告)日：2010-09-30
申请号：DE602007008546
申请日：2007-02-15
申请人： NXP BV
发明人： TUYLS PIM , VERTREGT MAARTEN , DE JONG HANS , LIST FRANS , WAGNER MATHIAS , ZACHARIASSE FRANK , MELS ARJAN
IPC分类号： G06F21/55

8. 发明专利

AT478391T 未知
公开(公告)号：AT478391T
公开(公告)日：2010-09-15
申请号：AT07705887
申请日：2007-02-15
申请人： NXP BV
发明人： TUYLS PIM , VERTREGT MAARTEN , DE JONG HANS , LIST FRANS , WAGNER MATHIAS , ZACHARIASSE FRANK , MELS ARJAN
IPC分类号： G06F21/55
摘要： It is described a method for providing an electronic key within an integrated circuit (100) including both a volatile memory (102) and a non-volatile memory (104). The described comprises starting up the integrated circuit (100), reading the logical state of predetermined data storage cells (102a) assigned to the volatile memory (102), which data storage cells (102a) are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and generating an electronic key by using the logical state of the predetermined data storage cells (102a). Preferably, the predetermined data storage cells (102a) are randomly distributed within the volatile memory (102). It is further described an integrated circuit (100) for providing an electronic key. The integrated circuit (100) comprises a volatile memory (102) comprising predetermined data storage cells (102a), which are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and a non-volatile memory (104) having information stored upon regarding the predetermined data storage cells (102a). Thereby, the electronic key is defined by the corresponding logical states of the predetermined data storage cells (102a).

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