专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

IL297397A Streamlining data processing optimizations for machine learning workloads 未知
公开(公告)号：IL297397A
公开(公告)日：2022-12-01
申请号：IL29739722
申请日：2022-10-18
申请人： IBM , QI ZHANG , PETR NOVOTNY , HONG MIN , RAVI NAIR , SHYAM RAMJI , LEI YU , TAKUYA NAKAIKE , MOTOHIRO KAWAHITO
发明人： QI ZHANG , PETR NOVOTNY , HONG MIN , RAVI NAIR , SHYAM RAMJI , LEI YU , TAKUYA NAKAIKE , MOTOHIRO KAWAHITO
IPC分类号： G06F16/25 , G06N20/00
摘要： Techniques for refinement of data pipelines are provided. An original file of serialized objects is received, and an original pipeline comprising a plurality of transformations is identified based on the original file. A first computing cost is determined for a first transformation of the plurality of transformations. The first transformation is modified using a predefined optimization, and a second cost of the modified first transformation is determined. Upon determining that the second cost is lower than the first cost, the first transformation is replaced, in the original pipeline, with the optimized first transformation.

2. 发明授权

US08990786B2 Program optimizing apparatus, program optimizing method, and program optimizing article of manufacture 有权
标题翻译：程序优化装置，程序优化方法和程序优化制造
公开(公告)号：US08990786B2
公开(公告)日：2015-03-24
申请号：US13307731
申请日：2011-11-30
申请人： Takuya Nakaike
发明人： Takuya Nakaike
IPC分类号： G06F9/45
CPC分类号： G06F8/4443 , G06F8/443 , G06F8/4441 , G06F8/447
摘要： An apparatus having a transactional memory enabling exclusive control to execute a transaction. The apparatus includes: a first code generating unit configured to interpret a program, and generate first code in which a begin instruction to begin a transaction and an end instruction to commit the transaction are inserted before and after an instruction sequence including multiple instructions to execute designated processing in the program; a second code generating unit configured to generate second code at a predetermined timing by using the multiple instructions according to the designated processing; and a code write unit configured to overwrite the instruction sequence of the first code with the second code or to write the second code to a part of the first code in the transaction.
摘要翻译：具有能够进行交易的排他控制的事务性存储器的装置。该装置包括：第一代码生成单元，被配置为解释程序，并且生成第一代码，其中开始交易的开始指令和提交交易的结束指令在包括执行指定的多个指令的指令序列之前和之后插入程序处理; 第二代码生成单元，被配置为通过使用根据指定处理的多个指令在预定定时生成第二代码; 以及代码写入单元，被配置为用第二代码覆盖第一代码的指令序列，或者将第二代码写入事务中的第一代码的一部分。

3. 发明申请

US20070256066A1 Profile-Based Global Live-Range Splitting 失效
标题翻译：基于档案的全球直播分割
公开(公告)号：US20070256066A1
公开(公告)日：2007-11-01
申请号：US11380833
申请日：2006-04-28
申请人： Takuya Nakaike , Tatsushi Inagaki , Hideaki Komatsu
发明人： Takuya Nakaike , Tatsushi Inagaki , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/433 , G06F8/441 , G06F8/443
摘要： A method and system are provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph.
摘要翻译：提供了一种方法和系统，用于在频繁执行的程序指令区域中分割变量的实时范围。变量的实时范围被分成多个子范围，每个子范围可以分配给不同的寄存器或溢出到存储器中。在频繁使用的代码区域中，通过在控制流程图中的每个连接点和分支点分割活动范围之后获得的简档信息来聚合生存范围，减少了经常使用的代码区域的数量。

4. 发明授权

US09032190B2 Recovering from an error in a fault tolerant computer system 有权
标题翻译：从容错计算机系统中的错误中恢复
公开(公告)号：US09032190B2
公开(公告)日：2015-05-12
申请号：US12859842
申请日：2010-08-20
申请人： Toshihiko Koju , Takuya Nakaike
发明人： Toshihiko Koju , Takuya Nakaike
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/38 , G06F11/14 , G06F11/16
CPC分类号： G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F11/1407 , G06F11/1479 , G06F11/1497 , G06F11/1629 , G06F11/1695
摘要： A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed.
摘要翻译：并行执行前导线程和后退线程。假设每个部分没有发生瞬态故障，则在该部分中推测性地执行一个系统，其中前导线和尾线最好分配给两个不同的核。此时，同时执行前导线程和后退线程，对线程本地区域执行缓冲操作，而不对共享存储器执行写入操作。当两个线程的相应执行结果相互匹配时，缓存到线程局部区域的内容被提交并写入共享存储器。当两个线程的相应执行结果彼此不匹配时，前导线程和后退线程将回滚到先前的提交点并重新执行。

5. 发明授权

US08555270B2 Profile-based global live-range splitting 失效
标题翻译：基于配置文件的全球实况分割
公开(公告)号：US08555270B2
公开(公告)日：2013-10-08
申请号：US11380833
申请日：2006-04-28
申请人： Takuya Nakaike , Tatsushi Inagaki , Hideaki Komatsu
发明人： Takuya Nakaike , Tatsushi Inagaki , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/433 , G06F8/441 , G06F8/443
摘要： A method and system are provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph.
摘要翻译：提供了一种方法和系统，用于在频繁执行的程序指令区域中分割变量的实时范围。变量的实时范围被分成多个子范围，每个子范围可以分配给不同的寄存器或溢出到存储器中。在频繁使用的代码区域中，通过在控制流程图中的每个连接点和分支点分割活动范围之后获得的简档信息来聚合生存范围，减少了经常使用的代码区域的数量。

6. 发明授权

US08386720B2 Method for allowing exclusive access to shared data 失效
标题翻译：允许独占访问共享数据的方法
公开(公告)号：US08386720B2
公开(公告)日：2013-02-26
申请号：US12553166
申请日：2009-09-03
申请人： Tatsushi Inagaki , Takuya Nakaike , Takeshi Ogasawara , Toshio Suganuma
发明人： Tatsushi Inagaki , Takuya Nakaike , Takeshi Ogasawara , Toshio Suganuma
IPC分类号： G06F12/14
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087
摘要： A method of allowing exclusive access to shared data by a computing device and a computer readable article embodying instructions for executing the method. The method includes: reading from a storage unit into a memory a program including a code for execution in a critical section and an instruction to write a value into or read a value from a shared data area in the memory; acquiring a lock on the critical section before start of a first instruction in the critical section; writing a value into a thread-local area in the memory in response to an instruction to write the value into the shared data area; writing into the shared data area the value written into the thread-local area upon completion of a final instruction in the critical section; and releasing the lock on the critical section, thereby allowing exclusive access to shared data.
摘要翻译：允许计算设备和体现用于执行该方法的指令的计算机可读文件对共享数据的独占访问的方法。该方法包括：从存储单元向存储器读取包括在临界区执行的代码的程序以及从存储器中的共享数据区写入值或读取值的指令; 在关键部分开始第一条指令之前，在关键部分获取锁定; 响应于将值写入共享数据区域的指令，将值写入存储器中的线程局部区域; 在关键部分完成最终指令后，将共享数据区写入到线程局部区域中的值; 并释放关键部分上的锁定，从而允许对共享数据的独占访问。

7. 发明授权

US08327342B2 Method of reducing logging code in a computing system 失效
标题翻译：减少计算系统中日志记录代码的方法
公开(公告)号：US08327342B2
公开(公告)日：2012-12-04
申请号：US12168206
申请日：2008-07-07
申请人： Hideaki Komatsu , Takuya Nakaike , Rei Odaira
发明人： Hideaki Komatsu , Takuya Nakaike , Rei Odaira
IPC分类号： G06F9/45
CPC分类号： G06F8/4435 , G06F8/443
摘要： A computing system for reducing logging code includes a virtual machine configured to control the flow of operations in the computing system and a compiler configured to receive bytecode instructions from the virtual machine and convert the bytecode instructions into machine instructions. The computing system also includes a compilation store configured to receive and store the machine instructions from the compiler and a recompilation store configured to receive and store recompiled machine instructions from the compiler. The system also includes a software transactional memory engine configured to receive instructions from the compilation store or, in the event that the recompilation store has recompiled machine instructions stored therein, from the recompilation store.
摘要翻译：用于减少日志记录代码的计算系统包括配置成控制计算系统中的操作流的虚拟机以及被配置为从虚拟机接收字节码指令并将该字节代码指令转换为机器指令的编译器。计算系统还包括配置存储器，其被配置为从编译器接收和存储机器指令，并且重新编译存储器被配置为从编译器接收和存储重新编译的机器指令。该系统还包括被配置为从重新编译存储器接收来自编译存储器的指令的软件事务内存引擎，或者在重新编译存储器已经重新编译存储在其中的机器指令的情况下。

8. 发明授权

US08266603B2 Technique for allocating register to variable for compiling 失效
标题翻译：分配寄存器到变量进行编译的技术
公开(公告)号：US08266603B2
公开(公告)日：2012-09-11
申请号：US12133349
申请日：2008-06-04
申请人： Tatsushi Inagaki , Hideaki Komatsu , Takuya Nakaike , Rei Odaira
发明人： Tatsushi Inagaki , Hideaki Komatsu , Takuya Nakaike , Rei Odaira
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： The present invention relates to allocating registers to variables in order to compile a program. In an embodiment of the present invention a compiler apparatus stores interference information indicating an interference relationship between variables, selects a register and allocates the register to each variables in accordance with a predetermined procedure, without allocating the same register to a set of variables having interference relationships. The compiler further replaces multiple variables having the same register allocated thereto with a new variable and generates an interference relationship by merging the interference relationships each concerning one of multiple variables. The compiler further updates interference information according to the generated interference relationship and allocates to each variable in the program using the new variable a register, selected in accordance with the predetermined procedure without allocating the same register to a set of variables having the interference relationships, based on the updated interference information.
摘要翻译：本发明涉及向变量分配寄存器以便编译程序。在本发明的实施例中，编译装置存储指示变量之间的干扰关系的干扰信息，选择寄存器并根据预定过程将寄存器分配给每个变量，而不将相同的寄存器分配给具有干扰关系的一组变量。编译器进一步用新的变量代替具有与其分配的相同寄存器的多个变量，并且通过合并关于多个变量之一的干扰关系来产生干扰关系。编译器根据产生的干扰关系进一步更新干扰信息，并使用新的变量将根据预定过程选择的寄存器分配给程序中的每个变量，而不将相同的寄存器分配给具有干扰关系的一组变量，关于更新的干扰信息。

9. 发明申请

US20120159461A1 PROGRAM OPTIMIZING APPARATUS, PROGRAM OPTIMIZING METHOD, AND PROGRAM OPTIMIZING ARTICLE OF MANUFACTURE 有权
标题翻译：程序优化设备，程序优化方法和程序优化制造文章
公开(公告)号：US20120159461A1
公开(公告)日：2012-06-21
申请号：US13307731
申请日：2011-11-30
申请人： Takuya Nakaike
发明人： Takuya Nakaike
IPC分类号： G06F9/45
CPC分类号： G06F8/4443 , G06F8/443 , G06F8/4441 , G06F8/447
摘要： An apparatus having a transactional memory enabling exclusive control to execute a transaction. The apparatus includes: a first code generating unit configured to interpret a program, and generate first code in which a begin instruction to begin a transaction and an end instruction to commit the transaction are inserted before and after an instruction sequence including multiple instructions to execute designated processing in the program; a second code generating unit configured to generate second code at a predetermined timing by using the multiple instructions according to the designated processing; and a code write unit configured to overwrite the instruction sequence of the first code with the second code or to write the second code to a part of the first code in the transaction.
摘要翻译：具有能够进行交易的排他控制的事务性存储器的装置。该装置包括：第一代码生成单元，被配置为解释程序，并且生成第一代码，其中开始交易的开始指令和提交交易的结束指令在包括执行指定的多个指令的指令序列之前和之后插入程序处理; 第二代码生成单元，被配置为通过使用根据指定处理的多个指令在预定定时生成第二代码; 以及代码写入单元，被配置为用第二代码重写第一代码的指令序列，或者将第二代码写入事务中的第一代码的一部分。

10. 发明授权

US07925471B2 Compiling method, apparatus, and program 失效
标题翻译：编译方法，装置和程序
公开(公告)号：US07925471B2
公开(公告)日：2011-04-12
申请号：US12190466
申请日：2008-08-12
申请人： Takuya Nakaike , Hideaki Komatsu
发明人： Takuya Nakaike , Hideaki Komatsu
IPC分类号： G05B13/02 , G05B13/00 , G06F19/00 , G06F17/40
CPC分类号： B25B21/00 , B25B21/026 , H04L67/02 , H04L67/322
摘要： Brings the response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining a response time goal which is a target value of the average response time; a section for calculating a predicted response time which is a predicted value of the average response time at the time point when a predetermined reference period has elapsed from setting an operation mode in the information processing apparatus, the operation mode being any of a plurality of operation modes which provide different throughputs; and a section for setting the operation mode in the information processing apparatus if predicted response time calculated by the predicted response time calculating section is less than goal.
摘要翻译：使Web服务器等的响应时间更接近目标值。控制由信息处理装置接收处理请求之间经过的平均响应时间和信息处理装置对处理请求的响应的控制器。控制器包括：用于获得作为平均响应时间的目标值的响应时间目标的部分; 用于计算预测响应时间的部分，所述预测响应时间是在从信息处理设备中的设置操作模式经过预定基准时段的时间点的平均响应时间的预测值，所述操作模式是多个操作提供不同吞吐量的模式; 以及如果由预测响应时间计算部计算出的预测响应时间小于目标，则在信息处理装置中设定操作模式的部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式