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1. 发明申请

US20070256066A1 Profile-Based Global Live-Range Splitting 失效
标题翻译：基于档案的全球直播分割
公开(公告)号：US20070256066A1
公开(公告)日：2007-11-01
申请号：US11380833
申请日：2006-04-28
申请人： Takuya Nakaike , Tatsushi Inagaki , Hideaki Komatsu
发明人： Takuya Nakaike , Tatsushi Inagaki , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/433 , G06F8/441 , G06F8/443
摘要： A method and system are provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph.
摘要翻译：提供了一种方法和系统，用于在频繁执行的程序指令区域中分割变量的实时范围。变量的实时范围被分成多个子范围，每个子范围可以分配给不同的寄存器或溢出到存储器中。在频繁使用的代码区域中，通过在控制流程图中的每个连接点和分支点分割活动范围之后获得的简档信息来聚合生存范围，减少了经常使用的代码区域的数量。

2. 发明授权

US08555270B2 Profile-based global live-range splitting 失效
标题翻译：基于配置文件的全球实况分割
公开(公告)号：US08555270B2
公开(公告)日：2013-10-08
申请号：US11380833
申请日：2006-04-28
申请人： Takuya Nakaike , Tatsushi Inagaki , Hideaki Komatsu
发明人： Takuya Nakaike , Tatsushi Inagaki , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/433 , G06F8/441 , G06F8/443
摘要： A method and system are provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph.
摘要翻译：提供了一种方法和系统，用于在频繁执行的程序指令区域中分割变量的实时范围。变量的实时范围被分成多个子范围，每个子范围可以分配给不同的寄存器或溢出到存储器中。在频繁使用的代码区域中，通过在控制流程图中的每个连接点和分支点分割活动范围之后获得的简档信息来聚合生存范围，减少了经常使用的代码区域的数量。

3. 发明授权

US08327342B2 Method of reducing logging code in a computing system 失效
标题翻译：减少计算系统中日志记录代码的方法
公开(公告)号：US08327342B2
公开(公告)日：2012-12-04
申请号：US12168206
申请日：2008-07-07
申请人： Hideaki Komatsu , Takuya Nakaike , Rei Odaira
发明人： Hideaki Komatsu , Takuya Nakaike , Rei Odaira
IPC分类号： G06F9/45
CPC分类号： G06F8/4435 , G06F8/443
摘要： A computing system for reducing logging code includes a virtual machine configured to control the flow of operations in the computing system and a compiler configured to receive bytecode instructions from the virtual machine and convert the bytecode instructions into machine instructions. The computing system also includes a compilation store configured to receive and store the machine instructions from the compiler and a recompilation store configured to receive and store recompiled machine instructions from the compiler. The system also includes a software transactional memory engine configured to receive instructions from the compilation store or, in the event that the recompilation store has recompiled machine instructions stored therein, from the recompilation store.
摘要翻译：用于减少日志记录代码的计算系统包括配置成控制计算系统中的操作流的虚拟机以及被配置为从虚拟机接收字节码指令并将该字节代码指令转换为机器指令的编译器。计算系统还包括配置存储器，其被配置为从编译器接收和存储机器指令，并且重新编译存储器被配置为从编译器接收和存储重新编译的机器指令。该系统还包括被配置为从重新编译存储器接收来自编译存储器的指令的软件事务内存引擎，或者在重新编译存储器已经重新编译存储在其中的机器指令的情况下。

4. 发明授权

US08266603B2 Technique for allocating register to variable for compiling 失效
标题翻译：分配寄存器到变量进行编译的技术
公开(公告)号：US08266603B2
公开(公告)日：2012-09-11
申请号：US12133349
申请日：2008-06-04
申请人： Tatsushi Inagaki , Hideaki Komatsu , Takuya Nakaike , Rei Odaira
发明人： Tatsushi Inagaki , Hideaki Komatsu , Takuya Nakaike , Rei Odaira
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： The present invention relates to allocating registers to variables in order to compile a program. In an embodiment of the present invention a compiler apparatus stores interference information indicating an interference relationship between variables, selects a register and allocates the register to each variables in accordance with a predetermined procedure, without allocating the same register to a set of variables having interference relationships. The compiler further replaces multiple variables having the same register allocated thereto with a new variable and generates an interference relationship by merging the interference relationships each concerning one of multiple variables. The compiler further updates interference information according to the generated interference relationship and allocates to each variable in the program using the new variable a register, selected in accordance with the predetermined procedure without allocating the same register to a set of variables having the interference relationships, based on the updated interference information.
摘要翻译：本发明涉及向变量分配寄存器以便编译程序。在本发明的实施例中，编译装置存储指示变量之间的干扰关系的干扰信息，选择寄存器并根据预定过程将寄存器分配给每个变量，而不将相同的寄存器分配给具有干扰关系的一组变量。编译器进一步用新的变量代替具有与其分配的相同寄存器的多个变量，并且通过合并关于多个变量之一的干扰关系来产生干扰关系。编译器根据产生的干扰关系进一步更新干扰信息，并使用新的变量将根据预定过程选择的寄存器分配给程序中的每个变量，而不将相同的寄存器分配给具有干扰关系的一组变量，关于更新的干扰信息。

5. 发明授权

US07925471B2 Compiling method, apparatus, and program 失效
标题翻译：编译方法，装置和程序
公开(公告)号：US07925471B2
公开(公告)日：2011-04-12
申请号：US12190466
申请日：2008-08-12
申请人： Takuya Nakaike , Hideaki Komatsu
发明人： Takuya Nakaike , Hideaki Komatsu
IPC分类号： G05B13/02 , G05B13/00 , G06F19/00 , G06F17/40
CPC分类号： B25B21/00 , B25B21/026 , H04L67/02 , H04L67/322
摘要： Brings the response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining a response time goal which is a target value of the average response time; a section for calculating a predicted response time which is a predicted value of the average response time at the time point when a predetermined reference period has elapsed from setting an operation mode in the information processing apparatus, the operation mode being any of a plurality of operation modes which provide different throughputs; and a section for setting the operation mode in the information processing apparatus if predicted response time calculated by the predicted response time calculating section is less than goal.
摘要翻译：使Web服务器等的响应时间更接近目标值。控制由信息处理装置接收处理请求之间经过的平均响应时间和信息处理装置对处理请求的响应的控制器。控制器包括：用于获得作为平均响应时间的目标值的响应时间目标的部分; 用于计算预测响应时间的部分，所述预测响应时间是在从信息处理设备中的设置操作模式经过预定基准时段的时间点的平均响应时间的预测值，所述操作模式是多个操作提供不同吞吐量的模式; 以及如果由预测响应时间计算部计算出的预测响应时间小于目标，则在信息处理装置中设定操作模式的部分。

6. 发明申请

US20090055634A1 COMPILING METHOD, APPARATUS, AND PROGRAM 失效
标题翻译：编译方法，设备和程序
公开(公告)号：US20090055634A1
公开(公告)日：2009-02-26
申请号：US12190466
申请日：2008-08-12
申请人： Takuya Nakaike , Hideaki Komatsu
发明人： Takuya Nakaike , Hideaki Komatsu
IPC分类号： G06F9/318
CPC分类号： B25B21/00 , B25B21/026 , H04L67/02 , H04L67/322
摘要： Brings response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining a response time goal which is a target value of the average response time; a section for calculating a predicted response time which is a predicted value of the average response time at the time point when a predetermined reference period has elapsed from setting an operation mode in the information processing apparatus, the operation mode being any of a plurality of operation modes which provide different throughputs; and a section for setting the operation mode in the information processing apparatus if predicted response time calculated by the predicted response time calculating section is less than goal.
摘要翻译：使Web服务器等的响应时间更接近目标值。控制由信息处理装置接收处理请求之间经过的平均响应时间和信息处理装置对处理请求的响应的控制器。控制器包括：用于获得作为平均响应时间的目标值的响应时间目标的部分; 用于计算预测响应时间的部分，所述预测响应时间是在从信息处理设备中的设置操作模式经过预定基准时段的时间点的平均响应时间的预测值，所述操作模式是多个操作提供不同吞吐量的模式; 以及如果由预测响应时间计算部计算出的预测响应时间小于目标，则在信息处理装置中设定操作模式的部分。

7. 发明申请

US20060095902A1 Information processing device and compiler 审中-公开
公开(公告)号：US20060095902A1
公开(公告)日：2006-05-04
申请号：US11255027
申请日：2005-10-20
申请人： Takuya Nakaike , Hideaki Komatsu , Seiichi Kawano
发明人： Takuya Nakaike , Hideaki Komatsu , Seiichi Kawano
IPC分类号： G06F9/45
CPC分类号： G06F1/3203 , G06F8/4432 , G06F9/4893 , Y02D10/24 , Y02D10/41
摘要： Devices, compilers and methods to reduce energy consumption associated with execution of a program by adjusting a computational capability of a CPU with higher accuracy than before. A device sets an appropriate computational capability to the CPU. It includes: changing a computational capability of the CPU every time each of a plurality of program areas included in the execution program is executed while the execution program is being executed, and measuring execution time each of the program areas; deciding an optimal computational capability required to execute the program area using the CPU, based on the execution time for each of the computational capabilities measured for the respective program areas; and performing setting of the optimal computational capability for executing the program area, which is to be used when executing the program area again in the course of executing the execution program, for each of the program areas.

8. 发明申请

US20100005457A1 METHOD OF REDUCING LOGGING CODE IN A COMPUTING SYSTEM 失效
标题翻译：降低计算系统中记录码的方法
公开(公告)号：US20100005457A1
公开(公告)日：2010-01-07
申请号：US12168206
申请日：2008-07-07
申请人： Hideaki Komatsu , Takuya Nakaike , Rei Odaira
发明人： Hideaki Komatsu , Takuya Nakaike , Rei Odaira
IPC分类号： G06F9/45
CPC分类号： G06F8/4435 , G06F8/443
摘要： A computing system for reducing logging code includes a virtual machine configured to control the flow of operations in the computing system and a compiler configured to receive bytecode instructions from the virtual machine and convert the bytecode instructions into machine instructions. The computing system also includes a compilation store configured to receive and store the machine instructions from the compiler and a recompilation store configured to receive and store recompiled machine instructions from the compiler. The system also includes a software transactional memory engine configured to receive instructions from the compilation store or, in the event that the recompilation store has recompiled machine instructions stored therein, from the recompilation store.
摘要翻译：用于减少日志记录代码的计算系统包括配置成控制计算系统中的操作流的虚拟机以及被配置为从虚拟机接收字节码指令并将该字节代码指令转换为机器指令的编译器。计算系统还包括配置存储器，其被配置为从编译器接收和存储机器指令，并且重新编译存储器被配置为从编译器接收和存储重新编译的机器指令。该系统还包括被配置为从重新编译存储器接收来自编译存储器的指令的软件事务内存引擎，或者在重新编译存储器已经重新编译存储在其中的机器指令的情况下。

9. 发明申请

US20090064112A1 TECHNIQUE FOR ALLOCATING REGISTER TO VARIABLE FOR COMPILING 失效
标题翻译：将注册分配给可编辑的变更技术
公开(公告)号：US20090064112A1
公开(公告)日：2009-03-05
申请号：US12133349
申请日：2008-06-04
申请人： Tatsushi Inagaki , Hideaki Komatsu , Takuya Nakaike , Rei Odaira
发明人： Tatsushi Inagaki , Hideaki Komatsu , Takuya Nakaike , Rei Odaira
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： The present invention relates to allocating registers to variables in order to compile a program. In an embodiment of the present invention a compiler apparatus stores interference information indicating an interference relationship between variables, selects a register and allocates the register to each variables in accordance with a predetermined procedure, without allocating the same register to a set of variables having interference relationships. The compiler further replaces multiple variables having the same register allocated thereto with a new variable and generates an interference relationship by merging the interference relationships each concerning one of multiple variables. The compiler further updates interference information according to the generated interference relationship and allocates to each variable in the program using the new variable a register, selected in accordance with the predetermined procedure without allocating the same register to a set of variables having the interference relationships, based on the updated interference information.
摘要翻译：本发明涉及向变量分配寄存器以便编译程序。在本发明的实施例中，编译装置存储指示变量之间的干扰关系的干扰信息，选择寄存器并根据预定的过程将寄存器分配给每个变量，而不向具有干扰关系的一组变量分配相同的寄存器。编译器进一步用新的变量代替具有与其分配的相同寄存器的多个变量，并且通过合并关于多个变量之一的干扰关系来产生干扰关系。编译器根据产生的干扰关系进一步更新干扰信息，并使用新的变量将根据预定过程选择的寄存器分配给程序中的每个变量，而不将相同的寄存器分配给具有干扰关系的一组变量，关于更新的干扰信息。

10. 发明授权

US07415383B2 Compiling method, apparatus, and program 失效
标题翻译：编译方法，装置和程序
公开(公告)号：US07415383B2
公开(公告)日：2008-08-19
申请号：US11291632
申请日：2005-12-01
申请人： Takuya Nakaike , Hideaki Komatsu
发明人： Takuya Nakaike , Hideaki Komatsu
IPC分类号： G06F19/00 , G06F17/40
CPC分类号： B25B21/00 , B25B21/026 , H04L67/02 , H04L67/322
摘要： Brings response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining a response time goal which is a target value of the average response time; a section for calculating a predicted response time which is a predicted value of the average response time at the time point when a predetermined reference period has elapsed from setting an operation mode in the information processing apparatus, the operation mode being any of a plurality of operation modes which provide different throughputs; and a section for setting the operation mode in the information processing apparatus if predicted response time calculated by the predicted response time calculating section is less than goal.
摘要翻译：使Web服务器等的响应时间更接近目标值。控制由信息处理装置接收处理请求之间经过的平均响应时间和信息处理装置对处理请求的响应的控制器。控制器包括：用于获得作为平均响应时间的目标值的响应时间目标的部分; 用于计算预测响应时间的部分，所述预测响应时间是在从信息处理设备中的设置操作模式经过预定基准时段的时间点的平均响应时间的预测值，所述操作模式是多个操作提供不同吞吐量的模式; 以及如果由预测响应时间计算部计算出的预测响应时间小于目标，则在信息处理装置中设定操作模式的部分。

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