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1. 发明申请

WO1992005493A1 SYSTEM EQUIPPED WITH PROCESSOR AND CACHE MEMORY, AND METHOD OF CONTROLLING SAID CACHE MEMORY 审中-公开
标题翻译：具有处理器和高速缓存存储器的系统以及控制上述高速缓存存储器的方法
公开(公告)号：WO1992005493A1
公开(公告)日：1992-04-02
申请号：PCT/JP1991001240
申请日：1991-09-18
申请人： FUJITSU LIMITED , TAKAHASHI, Hiromasa , IINO, Hideyuki
发明人： FUJITSU LIMITED
IPC分类号： G06F12/08
CPC分类号： G06F12/0877
摘要： A system comprising a cache memory (2) connected to a processor (1) and a main storage (3), wherein the processor includes means 1A for outputting a discrimination signal S designating whether the access to be made to the cache memory is a data access of continuous addresses or a data access of discontinuous addresses, and the cache memory (2) includes means 2A for handling errors in its operation on the basis of the outputted discrimination signal. During access to data of discontinuous addresses, control is so made as to suppress unnecessary accesses to the main storage. In this way, penality at the time of a failure of a cache operation is reduced and eventually, efficiency of the system can be improved as a whole by accomplishing a high speed operation

2. 发明申请

WO1992003791A1 MEMORY ACCESS SYSTEM 审中-公开
标题翻译：存储器访问系统
公开(公告)号：WO1992003791A1
公开(公告)日：1992-03-05
申请号：PCT/JP1991001124
申请日：1991-08-23
申请人： FUJITSU LIMITED , IINO, Hideyuki , TAKAHASHI, Hiromasa
发明人： FUJITSU LIMITED
IPC分类号： G06F12/06
CPC分类号： G06F12/0607 , G06F12/06 , G06F13/4243
摘要： An access memory system according to pipeline processing realizing an access to both microprocessors operated by 2 clocks per cycle and 1 clock per cycle. This method improves the access speed of the main memory while keeping flexibility, wherein a transition request signal for the pipe line is received to generate a control signal continuing by the number of cycles corresponding to at least the number of first-out addresses of the pipeline from immediately after start of pipeline operation and a display signal for displaying the completion of data access to banks. Then, while either of these two signals is generated, an address latch signal synchronizing with a clock signal is generated, the address latch signal is distributed to each bank, and data access is executed at a high speed.

3. 发明申请

WO1997038367A1 DISK DRIVE AND COMPUTER 审中-公开
标题翻译：磁盘驱动器和计算机
公开(公告)号：WO1997038367A1
公开(公告)日：1997-10-16
申请号：PCT/JP1997001204
申请日：1997-04-09
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM, LTD. , HAGIWARA, Mitsuo , TAKAHASHI, Hiromasa , YAMATO, Satoshi , SHIBASAKI, Nobuo , YOTSUTANI, Mitsuo , ISHII, Tsutomu
发明人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM, LTD.
IPC分类号： G06F09/06
CPC分类号： G06F3/0614 , G06F3/0623 , G06F3/0632 , G06F3/0644 , G06F3/0658 , G06F3/0674 , G06F3/0676 , G06F3/0677 , G06F8/65 , G06F9/4401
摘要： A microcomputer (5) constituted in an integrated circuit including an electrically erasable programmable nonvolatile memory (56) and a central processing unit (51) is adopted for controlling a disk drive (2). The memory (56) stores an application program, such as a recorded information reproduction control program in an application program area (561) and a reboot program which is utilized to update the application program in a reboot program area (560). The processor (51) rewrites all or part of the application program by executing the reboot program according to an application program rewriting command supplied from the outisde. Therefore, all or part of the application program stored in the memory (56) can be rewritten even after the microcomputer (5) is mounted on a disk drive. Since the reboot program area is not rewritten, the reprogram of the application program area is restarted immediately after the reboot program is executed again even when the reprogramming of the nonvolatile memory is interrupted due to abnormality.
摘要翻译：采用包括电可擦除可编程非易失性存储器（56）和中央处理单元（51）的集成电路中的微计算机（5）来控制磁盘驱动器（2）。存储器（56）将诸如记录信息再现控制程序之类的应用程序存储在应用程序区域（561）中，并且重新启动程序用于在重新启动程序区域（560）中更新应用程序。处理器（51）通过根据从outisde提供的应用程序重写命令执行重新启动程序来重写应用程序的全部或部分。因此，即使在微型计算机（5）安装在磁盘驱动器上之后，也可以重写存储在存储器（56）中的应用程序的全部或一部分。由于重新启动程序区域不被重写，所以即使非易失性存储器的重新编程由于异常而被中断，也会立即重新启动应用程序区域的重新编程。

4. 发明申请

WO1994006075A1 METHOD AND APPARATUS FOR NON-NUMERIC CHARACTER DISCRIMINATION 审中-公开
标题翻译：非数字字符识别的方法和装置
公开(公告)号：WO1994006075A1
公开(公告)日：1994-03-17
申请号：PCT/JP1993001232
申请日：1993-08-31
申请人： FUJITSU LIMITED , YANAGIDA, Masahiro , TAKAHASHI, Hiromasa , TACHIBANA, Osamu
发明人： FUJITSU LIMITED
IPC分类号： G06F07/00
CPC分类号： G06F7/483
摘要： It is made possible during the processing of an IEEE type binary floating point number irrespective of precision to judge whether it is a non-numeric character. An IEEE type binary floating point number having a sign portion, an exponent portion and a mantissa portion, is defined as a non-numeric character under the conditions that the bits of the exponent portion are all '1' and that not all the bits of the mantissa portion are '0'. When the character has the maximum precision, the data thereon are used as they are as interior expressed type data. When the character does not have the maximum precision, on the other hand, the sign portion is used as it is; the exponent portion is expanded to the maximum precision by filling the vacant bit(s) with '1'; and the mantissa portion is expanded to the maximum precision by filling the vacant bit(s) with '0'. The results of this conversion are used as interior expressed type data. The interior expressed type data, all as data of maximum precision, are subjected collectively to non-numeric character discrimination.
摘要翻译：在IEEE类型的二进制浮点数的处理期间，无论精度如何，都可以判断它是否是非数字字符。具有符号部分，指数部分和尾数部分的IEEE类型的二进制浮点数在指数部分的位全部为“1”的条件下被定义为非数字字符，并且不是全部位尾数部分为“0”。当字符具有最大精度时，将其上的数据原样用作内部表示类型数据。另一方面，当字符不具有最大精度时，符号部分被原样使用; 通过用'1'填充空位来将指数部分扩展到最大精度; 并且通过用“0”填充空位来将尾数部分扩展到最大精度。该转换的结果用作内部表示类型的数据。内部表示类型数据，全部作为最大精度的数据，共同受到非数字字符识别。

5. 发明申请

WO1992006432A1 DEVICE FOR CONTROLLING BUS 审中-公开
标题翻译：控制总线的装置
公开(公告)号：WO1992006432A1
公开(公告)日：1992-04-16
申请号：PCT/JP1991001342
申请日：1991-10-03
申请人： FUJITSU LIMITED , IINO, Hideyuki , TAKAHASHI, Hiromasa
发明人： FUJITSU LIMITED
IPC分类号： G06F13/362
CPC分类号： G06F13/364 , G06F13/362
摘要： A device for controlling buses which reduces the time for waiting bus accesses and particularly improves the performance of an arithmetic processing means which frequently access a main memory. The device is provided with a means (12b) for generating a bus request signals in response to the requests from an arithmetic processing means (12a), a means (e) for arbitrating the rights of using the buses which arbitrates the rights of using the buses in response to the bus request signals and informs the unit of the result, a means (12c) for performing bus accesses using the means (12a) as a bus master after receiving the information on the right of using the buses, and a hold indicating means (12d) for making the bus request signals held while a predetermined hold signal is asserted and a predetermined release signal is negated.

6. 发明申请

WO1992005494A1 SYSTEM EQUIPPED WITH PROCESSOR AND METHOD OF CONVERTING ADDRESSES IN SAID SYSTEM 审中-公开
标题翻译：具有处理器的系统和在系统中转换地址的方法
公开(公告)号：WO1992005494A1
公开(公告)日：1992-04-02
申请号：PCT/JP1991001261
申请日：1991-09-20
申请人： FUJITSU LIMITED , TAKAHASHI, Hiromasa , IINO, Hideyuki
发明人： FUJITSU LIMITED
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/0207
摘要： A system comprising a processor (1) for converting addresses by the use of a multistage conversion table for making memory access and a main storage (2), wherein the processor includes first memory means (3) for storing part of the multistage conversion table, and the main storage (2) includes second memory means (4) for storing the rest of the conversion table. Address conversion from a logical address LA to a physical address PA can be made rapidly through a relatively simple control by searching the conversion table of the second memory means by the use of the entry address obtained by searching the conversion table of the first memory means, and eventually, performance of the overall system can be improved.

7. 发明专利

JP2005213879A Drain pipe construction method and ground drilling unit 有权
标题翻译：排水管道施工方法和地下钻井单元
公开(公告)号：JP2005213879A
公开(公告)日：2005-08-11
申请号：JP2004021958
申请日：2004-01-29
申请人： Kidoh Construction Co Ltd , Takahashi Hiromasa , Takku:Kk , Tasuku:Kk , 有限会社タック , 株式会社タスク , 機動建設工業株式会社 , 高橋弘昌
发明人： NAKANO MASAAKI
IPC分类号： E02D3/10 , E02D27/34
摘要： PROBLEM TO BE SOLVED: To properly implement a drain pipe construction method even in a working environment such as the premise of an existing house wherein a sufficient construction space can be hardly secured, wherein there is a risk of an adverse affect on a surrounding environment, and wherein large-scale equipment can be hardly used.
SOLUTION: This construction method comprises: a step (a) of arranging a ground drilling unit 20 in a drain pipe 10, and arranging a drilling bit 30 at the leading end of the drain pipe 10 and the drilling unit 20; a step (b) of generating forced vibration by the drilling unit 20 so as to fluidize the ground E adjacent to the outside via the drain pipe 10 and the drilling bit 30; a step (c) of making the drilling unit 20 and the drain pipe 10 penetrate into the ground E in a state that the drilling bit 30 is in a leading position so that the drain pipe 10 can be buried in the ground E; and a step (d) of removing the drilling device 20 from the buried drain pipe 10.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使在诸如现有房屋的前提下的工作环境中也可以适当地实施排水管施工方法，其中可能难以确保足够的施工空间，其中存在对周边环境，大型设备难以使用。解决方案：该施工方法包括：在排水管10中设置钻井单元20的步骤（a），在排水管10和钻井单元20的前端设置钻头30; 由钻井单元20产生强制振动以通过排水管10和钻头30使靠近外部的地面E流化的步骤（b）; 在钻头30处于引导位置的状态下使钻井单元20和排水管10穿入地面E的步骤（c），使得排水管10可以埋在地面E中; 以及从埋地排水管10移除钻孔装置20的步骤（d）。版权所有（C）2005，JPO＆NCIPI

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