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    • 6. 发明授权
    • Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device
    • 数据输入电路,用于减少半导体器件中提取信号与多个数据之间的负载差异
    • US06734707B2
    • 2004-05-11
    • US10340831
    • 2003-01-13
    • Ho-young SongKyu-hyoun KimSu-bong Jang
    • Ho-young SongKyu-hyoun KimSu-bong Jang
    • H03M700
    • G11C7/1093G11C7/1072G11C7/1087G11C2207/105G11C2207/108
    • A data input circuit for use in a semiconductor device, the data input circuit reducing a load difference between a fetch signal and a plurality of groups of data. The data input circuit includes first through Nth latching units for latching each one of N groups of data in response to a reference clock, respectively (N is a natural number greater than 2), and a bus for transmitting the reference clock and the N groups of data to the first through Nth latching units. Each of the first through Nth latching units includes a clock buffer for buffering the reference clock; a data buffer for buffering a corresponding group of data of the N groups of data; N−1 dummy elements for respectively receiving each one of the N groups of data, except for the group of data input to the data buffer; and latches for latching data output from the data buffer in synchronization with a signal output from the clock buffer. Use of the data input circuit makes a load on a reference clock the same or substantially the same as that on each group of data. Therefore, a load difference between the reference clock and each group of data is reduced to reduce a skew therebetween.
    • 一种用于半导体器件的数据输入电路,所述数据输入电路减小了获取信号与多组数据之间的负载差异。 数据输入电路包括第一到第N个锁存单元,用于分别响应于参考时钟(N是大于2的自然数)来锁存N组数据中的每一个,以及用于发送参考时钟和 N组数据到第一至第N个锁存单元。 每个第一至第N个锁存单元包括用于缓冲参考时钟的时钟缓冲器; 数据缓冲器,用于缓冲N组数据的相应的数据组; N-1个虚拟元素,用于分别接收N组数据中的每一个,除了输入到数据缓冲器的数据组之外; 以及用于锁存从数据缓冲器输出的数据与从时钟缓冲器输出的信号同步的锁存器。 使用数据输入电路使参考时钟上的负载与每组数据上的相同或基本相同。 因此,参考时钟与每组数据之间的负载差减小,以减少它们之间的偏斜。