专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09552206B2 Integrated circuit with control node circuitry and processing circuitry 有权
标题翻译：具有控制节点电路和处理电路的集成电路
公开(公告)号：US09552206B2
公开(公告)日：2017-01-24
申请号：US13232774
申请日：2011-09-14
申请人： William M. Johnson , Murali S. Chinnakonda , Jeffrey L. Nye , Toshio Nagata , John W. Glotzbach , Hamid R. Sheikh , Ajay Jayaraj , Stephen Busch , Shalini Gupta , Robert J.P. Nychka , David H. Bartley , Ganesh Sundararajan
发明人： William M. Johnson , Murali S. Chinnakonda , Jeffrey L. Nye , Toshio Nagata , John W. Glotzbach , Hamid R. Sheikh , Ajay Jayaraj , Stephen Busch , Shalini Gupta , Robert J.P. Nychka , David H. Bartley , Ganesh Sundararajan
IPC分类号： G06F15/16 , G06F15/80 , G06F9/30 , G06F9/355 , G06F9/38 , G06F9/45
CPC分类号： G06F9/30076 , G06F8/40 , G06F9/30 , G06F9/30054 , G06F9/30101 , G06F9/3012 , G06F9/355 , G06F9/3552 , G06F9/3853 , G06F9/3887 , G06F9/3891 , G06F15/16 , G06F15/80 , G06F15/8053
摘要： Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.
摘要翻译：传统上，在多核系统中提供并行处理非常困难。然而，这里提供了一种系统，其中串行源代码被自动转换为并行源代码，并且“即时”重新配置处理集群，以根据存储器和计算资源的分配来容纳并行化代码。因此，处理集群及其相应的系统编程工具提供可以对从用户透明的串行程序执行并行处理的系统。通常，连接到主处理器的地址和数据引线的控制节点使用消息来控制处理集群中的数据的处理。集群包括并行处理器的节点，共享功能存储器，全局加载/存储以及所有通过消息总线连接到控制节点的硬件加速器。交叉开关数据互连将数据路由到与消息总线分离的集群电路。

2. 发明授权

US08749667B2 System and method for maintaining maximum input rate while up-scaling an image vertically 有权
标题翻译：用于在垂直地扩大图像的同时保持最大输入速率的系统和方法
公开(公告)号：US08749667B2
公开(公告)日：2014-06-10
申请号：US12971675
申请日：2010-12-17
申请人： Frederic J. Noraz , Shashank Dabral , Stephen Busch
发明人： Frederic J. Noraz , Shashank Dabral , Stephen Busch
IPC分类号： H04N5/262
CPC分类号： H04N5/2628 , G06T3/4023
摘要： An example embodiment provides a resizer in an image processing system. The resizer includes a receiving module that receives pixel data representative of an image. A triple line buffer is coupled to the receiving module that stores the pixel data in response to a write control signal from control logic. The triple line buffer is operated as a circular buffer. The resizer further includes a resizer core that reads pixel data from the triple line buffer in response to a read control signal from the control logic. The pixel data is replicated to up-scale the image vertically according to a vertical up-scale ratio such that the resizer achieves a maximum input data rate and also eliminates an overflow condition in the resizer. The vertical up-scale ratio is a fraction.
摘要翻译：示例性实施例在图像处理系统中提供调整器。调整器包括接收代表图像的像素数据的接收模块。三线缓冲器耦合到接收模块，该接收模块响应于来自控制逻辑的写控制信号而存储像素数据。三线缓冲器作为循环缓冲器运行。调整器还包括响应于来自控制逻辑的读取控制信号从三行缓冲器读取像素数据的调整器内核。像素数据被复制以根据垂直上标比例垂直地升高图像，使得resizer达到最大输入数据速率，并且还消除了调整器中的溢出状况。垂直上升比例是一小部分。

3. 发明申请

US20120131309A1 HIGH-PERFORMANCE, SCALABLE MUTLICORE HARDWARE AND SOFTWARE SYSTEM 有权
标题翻译：高性能，可扩展的MUTLICORE硬件和软件系统
公开(公告)号：US20120131309A1
公开(公告)日：2012-05-24
申请号：US13232774
申请日：2011-09-14
申请人： William M. Johnson , Murali S. Chinnakonda , Jeffrey L. Nye , Toshio Nagata , John W. Glotzbach , Hamid R. Sheikh , Ajay Jayaraj , Stephen Busch , Shalini Gupta , Robert J.P. Nychka , David H. Bartley , Ganesh Sundararajan
发明人： William M. Johnson , Murali S. Chinnakonda , Jeffrey L. Nye , Toshio Nagata , John W. Glotzbach , Hamid R. Sheikh , Ajay Jayaraj , Stephen Busch , Shalini Gupta , Robert J.P. Nychka , David H. Bartley , Ganesh Sundararajan
IPC分类号： G06F9/22 , G06F9/46
CPC分类号： G06F9/30076 , G06F8/40 , G06F9/30 , G06F9/30054 , G06F9/30101 , G06F9/3012 , G06F9/355 , G06F9/3552 , G06F9/3853 , G06F9/3887 , G06F9/3891 , G06F15/16 , G06F15/80 , G06F15/8053
摘要： Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system in provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user.
摘要翻译：传统上，在多核系统中提供并行处理非常困难。然而，这里提供了一种系统，其中串行源代码被自动转换为并行源代码，并且处理集群“即时”重新配置，以根据存储器和计算资源的分配来适应并行化代码。因此，处理集群及其相应的系统编程工具提供可以对从用户透明的串行程序执行并行处理的系统。

4. 发明申请

US20120026367A1 SYSTEM AND METHOD FOR MAINTAINING MAXIMUM INPUT RATE WHILE UP-SCALING AN IMAGE VERTICALLY 有权
标题翻译：用于维持垂直上升图像时维持最大输入速率的系统和方法
公开(公告)号：US20120026367A1
公开(公告)日：2012-02-02
申请号：US12971675
申请日：2010-12-17
申请人： Frederic J. Noraz , Shashank Dabral , Stephen Busch
发明人： Frederic J. Noraz , Shashank Dabral , Stephen Busch
IPC分类号： H04N5/262 , H04N9/74
CPC分类号： H04N5/2628 , G06T3/4023
摘要： An example embodiment provides a resizer in an image processing system. The resizer includes a receiving module that receives pixel data representative of an image. A triple line buffer is coupled to the receiving module that stores the pixel data in response to a write control signal from control logic. The triple line buffer is operated as a circular buffer. The resizer further includes a resizer core that reads pixel data from the triple line buffer in response to a read control signal from the control logic. The pixel data is replicated to up-scale the image vertically according to a vertical up-scale ratio such that the resizer achieves a maximum input data rate and also eliminates an overflow condition in the resizer. The vertical up-scale ratio is a fraction.
摘要翻译：示例性实施例在图像处理系统中提供调整器。调整器包括接收代表图像的像素数据的接收模块。三线缓冲器耦合到接收模块，该接收模块响应于来自控制逻辑的写控制信号而存储像素数据。三线缓冲器作为循环缓冲器运行。调整器还包括响应于来自控制逻辑的读取控制信号从三行缓冲器读取像素数据的调整器内核。像素数据被复制以根据垂直上标比例垂直地升高图像，使得resizer达到最大输入数据速率，并且还消除了调整器中的溢出状况。垂直上升比例是一小部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式