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1. 发明授权

US07925859B2 Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor 有权
标题翻译：多线程微处理器中的三层翻译后备缓冲层次结构
公开(公告)号：US07925859B2
公开(公告)日：2011-04-12
申请号：US12495375
申请日：2009-06-30
申请人： Soumya Banerjee , Michael Gottlieb Jensen , Ryan C. Kinter
发明人： Soumya Banerjee , Michael Gottlieb Jensen , Ryan C. Kinter
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.
摘要翻译：提供了同时执行多个指令线程的多线程处理器中的三层TLB架构。宏TLB缓存所有线程的内存页面的地址转换信息。微型TLB缓存缓存在宏TLB中的存储器页面的子集的翻译信息。用于每个线程的相应的nano-TLB仅缓存针对相应线程的转换信息。纳米TLB还包括替换信息以指示nano-TLB / micro-TLB中的哪些条目最近使用相应线程的翻译信息。根据替换信息，如果从微型TLB迁移，最近使用的信息被复制到nano-TLB。

2. 发明授权

US07558939B2 Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor 有权
标题翻译：多线程微处理器中的三层翻译后备缓冲层次结构
公开(公告)号：US07558939B2
公开(公告)日：2009-07-07
申请号：US11075041
申请日：2005-03-08
申请人： Soumya Banerjee , Michael Gottlieb Jensen , Ryan C. Kinter
发明人： Soumya Banerjee , Michael Gottlieb Jensen , Ryan C. Kinter
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.
摘要翻译：提供了同时执行多个指令线程的多线程处理器中的三层TLB架构。宏TLB缓存所有线程的内存页面的地址转换信息。微型TLB缓存缓存在宏TLB中的存储器页面的子集的翻译信息。用于每个线程的相应的nano-TLB仅缓存针对相应线程的转换信息。纳米TLB还包括替换信息，以指示nano-TLB / micro-TLB中的哪些条目最近使用相应线程的翻译信息。根据替换信息，如果从微型TLB迁移，最近使用的信息被复制到nano-TLB。

3. 发明申请

US20060179276A1 Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor 有权
标题翻译： Fetch Director采用基于桶式增量器的循环设备，用于多线程微处理器
公开(公告)号：US20060179276A1
公开(公告)日：2006-08-10
申请号：US11087063
申请日：2005-03-22
申请人： Soumya Banerjee , Michael Jensen
发明人： Soumya Banerjee , Michael Jensen
IPC分类号： G06F9/40
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3814
摘要： A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread. In one embodiment threads with an empty instruction buffer are selected at highest priority; a last dispatched but not fetched thread at middle priority; all other threads at lowest priority. The threads are selected round-robin within the highest and lowest priorities.
摘要翻译：公开了并行执行N线程指令的多线程微处理器中的提取指导者。 N线程请求从指令高速缓存获取指令。在给定的选择周期中，某些线程可能没有请求获取指令。提取指导器包括用于以循环方式选择线程之一以将其提取地址提供给指令高速缓存的电路。 1位左电路通过第二加数旋转地增加第一加数，以产生与第一加数的反相并联的和，以产生指示下一个选择的线程的1-hot向量。第一个加数是一个N位向量，如果相应的线程请求从指令高速缓存中获取指令，则每个位都为假。第二个加法是指示最后选择的线程的1-hot向量。在一个实施例中，以最高优先级选择具有空指令缓冲器的线程; 中间优先级的最后发送但未获取的线程; 所有其他线程的优先级最低。线程在最高和最低优先级内选择循环。

4. 发明授权

US08151093B2 Software programmable hardware state machines 有权
标题翻译：软件可编程硬件状态机
公开(公告)号：US08151093B2
公开(公告)日：2012-04-03
申请号：US11517569
申请日：2006-09-08
申请人： Soumya Banerjee , Gideon D. Intrater , Michael Gottlieb Jensen
发明人： Soumya Banerjee , Gideon D. Intrater , Michael Gottlieb Jensen
IPC分类号： G06F9/00
CPC分类号： G06F11/2236
摘要： The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. In example embodiments, processors, systems and methods are provided to prevent an unwanted change in architectural state from occurring as a result of execution of a specific sequence of instruction types. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor. The desired action may be preventing the dispatch of a next instruction, flushing a pipeline, clearing an instruction fetch buffer, generating an exception etc. The processor core further comprises a programmable fix register. In an embodiment, the control logic generates the control signals based on control bits stored in the fix register.
摘要翻译：本发明提供了用于检测处理器中的错误原因的软件可编程硬件状态机，并防止发生错误。在示例实施例中，提供了处理器，系统和方法，以防止由于执行特定指令序列类型而导致架构状态的不期望的改变。提供了一种处理器核心，其包括执行单元，可编程屏蔽寄存器和存储表示分配给执行单元的指令的值的缓冲器。处理器核心还包括控制逻辑以确定掩模寄存器中的序列与缓冲器中的序列之间是否存在匹配，并且在检测到匹配时，产生控制信号以执行期望的动作。期望的操作防止对处理器的架构状态发生不期望的改变。期望的动作可能是阻止下一条指令的调度，冲洗流水线，清除指令获取缓冲区，产生异常等。处理器核心还包括可编程固定寄存器。在一个实施例中，控制逻辑基于存储在定位寄存器中的控制位产生控制信号。

5. 发明授权

US08103987B2 System and method for managing the design and configuration of an integrated circuit semiconductor design 有权
标题翻译：用于管理集成电路半导体设计的设计和配置的系统和方法
公开(公告)号：US08103987B2
公开(公告)日：2012-01-24
申请号：US11684156
申请日：2007-03-09
申请人： Soumya Banerjee , Todd Michael Bezenek , Clement Tse
发明人： Soumya Banerjee , Todd Michael Bezenek , Clement Tse
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A system and methods that facilitate the design process and minimize the time and effort required to complete the design and fabrication of an integrated circuits (IC) are described. The system and method utilize a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the device. The system and method securely maintains synthesizable RTL on a server in a data center while providing designers access to portions of the mechanism by way of a network portal.
摘要翻译：描述了促进设计过程并最小化完成集成电路（IC）的设计和制造所需的时间和精力的系统和方法。系统和方法利用多个存储库，规则引擎和设计和验证工具来分析工作量并自动产生硬化的GDSII描述或设备的其他表示。该系统和方法在数据中心的服务器上安全地维护可合成的RTL，同时通过网络门户为设计人员提供对机构部分的访问。

6. 发明授权

US07774723B2 Protecting trade secrets during the design and configuration of an integrated circuit semiconductor design 有权
标题翻译：在集成电路半导体设计的设计和配置过程中保护商业秘密
公开(公告)号：US07774723B2
公开(公告)日：2010-08-10
申请号：US11684205
申请日：2007-03-09
申请人： Soumya Banerjee
发明人： Soumya Banerjee
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A system and method for facilitating the design process of an integrated circuits (IC) is described. The system and method utilizes a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the IC. Synthesizable RTL is securely maintained on a server in a data center while providing designers graphical access to customizable IP block by way of a network portal.
摘要翻译：描述了用于促进集成电路（IC）的设计过程的系统和方法。该系统和方法利用多个存储库，规则引擎和设计和验证工具来分析工作负载并自动产生硬化的GDSII描述或IC的其它表示。可合成的RTL被安全地维护在数据中心的服务器上，同时通过网络门户为设计师提供图形化访问可定制的IP块。

7. 发明申请

US20090327649A1 Three-Tiered Translation Lookaside Buffer Hierarchy in a Multithreading Microprocessor 有权
标题翻译：多线程微处理器中的三层翻译后备缓冲层次结构
公开(公告)号：US20090327649A1
公开(公告)日：2009-12-31
申请号：US12495375
申请日：2009-06-30
申请人： Soumya BANERJEE , Michael Gottlieb Jensen , Ryan C. Kinter
发明人： Soumya BANERJEE , Michael Gottlieb Jensen , Ryan C. Kinter
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.
摘要翻译：提供了同时执行多个指令线程的多线程处理器中的三层TLB架构。宏TLB缓存所有线程的内存页面的地址转换信息。微型TLB缓存缓存在宏TLB中的存储器页面的子集的翻译信息。用于每个线程的相应的nano-TLB仅缓存针对相应线程的转换信息。纳米TLB还包括替换信息以指示nano-TLB / micro-TLB中的哪些条目最近使用相应线程的翻译信息。根据替换信息，如果从微型TLB迁移，最近使用的信息被复制到nano-TLB。

8. 发明申请

US20080222589A1 Protecting Trade Secrets During the Design and Configuration of an Integrated Circuit Semiconductor Design 有权
标题翻译：在集成电路半导体设计的设计和配置过程中保护商业秘密
公开(公告)号：US20080222589A1
公开(公告)日：2008-09-11
申请号：US11684205
申请日：2007-03-09
申请人： Soumya Banerjee
发明人： Soumya Banerjee
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A system and method for facilitating the design process of an integrated circuits (IC) is described. The system and method utilizes a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the IC. Synthesizable RTL is securely maintained on a server in a data center while providing designers graphical access to customizable IP block by way of a network portal.
摘要翻译：描述了用于促进集成电路（IC）的设计过程的系统和方法。该系统和方法利用多个存储库，规则引擎和设计和验证工具来分析工作负载并自动产生硬化的GDSII描述或IC的其它表示。可合成的RTL被安全地维护在数据中心的服务器上，同时通过网络门户为设计师提供图形化访问可定制的IP块。

9. 发明申请

US20080065868A1 Software programmable hardware state machines 有权
标题翻译：软件可编程硬件状态机
公开(公告)号：US20080065868A1
公开(公告)日：2008-03-13
申请号：US11517569
申请日：2006-09-08
申请人： Soumya Banerjee , Gideon D. Intrater , Michael Gottlieb Jensen
发明人： Soumya Banerjee , Gideon D. Intrater , Michael Gottlieb Jensen
IPC分类号： G06F9/44
CPC分类号： G06F11/2236
摘要： The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. In example embodiments, processors, systems and methods are provided to prevent an unwanted change in architectural state from occurring as a result of execution of a specific sequence of instruction types. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor. The desired action may be preventing the dispatch of a next instruction, flushing a pipeline, clearing an instruction fetch buffer, generating an exception etc. The processor core further comprises a programmable fix register. In an embodiment, the control logic generates the control signals based on control bits stored in the fix register.
摘要翻译：本发明提供了用于检测处理器中的错误原因的软件可编程硬件状态机，并防止发生错误。在示例实施例中，提供了处理器，系统和方法，以防止由于执行特定指令序列类型而导致架构状态的不期望的改变。提供了一种处理器核心，其包括执行单元，可编程屏蔽寄存器和存储表示分配给执行单元的指令的值的缓冲器。处理器核心还包括控制逻辑以确定掩模寄存器中的序列与缓冲器中的序列之间是否存在匹配，并且在检测到匹配时，产生控制信号以执行期望的动作。期望的操作防止对处理器的架构状态发生不期望的改变。期望的动作可能是阻止下一条指令的调度，冲洗流水线，清除指令获取缓冲区，产生异常等。处理器核心还包括可编程固定寄存器。在一个实施例中，控制逻辑基于存储在定位寄存器中的控制位产生控制信号。

10. 发明申请

US20060206686A1 Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor 有权
公开(公告)号：US20060206686A1
公开(公告)日：2006-09-14
申请号：US11075041
申请日：2005-03-08
申请人： Soumya Banerjee , Michael Jensen , Ryan Kinter
发明人： Soumya Banerjee , Michael Jensen , Ryan Kinter
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.

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