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1. 发明授权

US08446770B2 Methods for programming nonvolatile memory devices 有权
标题翻译：非易失性存储器件编程方法
公开(公告)号：US08446770B2
公开(公告)日：2013-05-21
申请号：US13468312
申请日：2012-05-10
申请人： Hyun-Sil Oh , Kitae Park , Soonwook Hwang
发明人： Hyun-Sil Oh , Kitae Park , Soonwook Hwang
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： Provided is a method for programming a nonvolatile memory device. The nonvolatile memory device includes a local word line to divide a memory cell string into a first area including a selected word line and a second area not including the selected word line. In the method, word lines of the first area are driven by a first pass voltage and word lines of the second area driven by a second pass voltage higher than the first pass voltage. A cell transistor corresponding to the local word line is turned off after the first pass voltage and the second pass voltage are applied. The selected word line is driven by a program voltage after the cell transistor is turned off.
摘要翻译：提供了一种用于对非易失性存储器件进行编程的方法。非易失性存储器件包括用于将存储单元串划分成包括所选字线的第一区域和不包括所选字线的第二区域的本地字线。在该方法中，第一区域的字线由第一通过电压和由比第一通过电压高的第二通过电压驱动的第二区域的字线驱动。在施加第一通过电压和第二通过电压之后，对应于本地字线的单元晶体管截止。在单元晶体管截止之后，所选字线由编程电压驱动。

2. 发明申请

US20100202215A1 Methods for Programming Nonvolatile Memory Devices 有权
标题翻译：非易失性存储器件编程方法
公开(公告)号：US20100202215A1
公开(公告)日：2010-08-12
申请号：US12701037
申请日：2010-02-05
申请人： Hyun-Sil Oh , Kitae Park , Soonwook Hwang
发明人： Hyun-Sil Oh , Kitae Park , Soonwook Hwang
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/0483
摘要： Provided is a method for programming a nonvolatile memory device. The nonvolatile memory device includes a local word line to divide a memory cell string into a first area including a selected word line and a second area not including the selected word line. In the method, word lines of the first area are driven by a first pass voltage and word lines of the second area driven by a second pass voltage higher than the first pass voltage. A cell transistor corresponding to the local word line is turned off after the first pass voltage and the second pass voltage are applied. The selected word line is driven by a program voltage after the cell transistor is turned off.
摘要翻译：提供了一种用于对非易失性存储器件进行编程的方法。非易失性存储器件包括用于将存储单元串划分成包括所选字线的第一区域和不包括所选字线的第二区域的本地字线。在该方法中，第一区域的字线由第一通过电压和由比第一通过电压高的第二通过电压驱动的第二区域的字线驱动。在施加第一通过电压和第二通过电压之后，对应于本地字线的单元晶体管截止。在单元晶体管截止之后，所选字线由编程电压驱动。

3. 发明授权

US08194455B2 Methods for programming nonvolatile memory devices 有权
标题翻译：非易失性存储器件编程方法
公开(公告)号：US08194455B2
公开(公告)日：2012-06-05
申请号：US12701037
申请日：2010-02-05
申请人： Hyun-Sil Oh , Kitae Park , Soonwook Hwang
发明人： Hyun-Sil Oh , Kitae Park , Soonwook Hwang
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： Provided is a method for programming a nonvolatile memory device. The nonvolatile memory device includes a local word line to divide a memory cell string into a first area including a selected word line and a second area not including the selected word line. In the method, word lines of the first area are driven by a first pass voltage and word lines of the second area driven by a second pass voltage higher than the first pass voltage. A cell transistor corresponding to the local word line is turned off after the first pass voltage and the second pass voltage are applied. The selected word line is driven by a program voltage after the cell transistor is turned off.
摘要翻译：提供了一种用于对非易失性存储器件进行编程的方法。非易失性存储器件包括用于将存储单元串划分成包括所选字线的第一区域和不包括所选字线的第二区域的本地字线。在该方法中，第一区域的字线由第一通过电压和由比第一通过电压高的第二通过电压驱动的第二区域的字线驱动。在施加第一通过电压和第二通过电压之后，对应于本地字线的单元晶体管截止。在单元晶体管截止之后，所选字线由编程电压驱动。

4. 发明申请

US20120218828A1 Methods for Programming Nonvolatile Memory Devices 有权
标题翻译：非易失性存储器件编程方法
公开(公告)号：US20120218828A1
公开(公告)日：2012-08-30
申请号：US13468312
申请日：2012-05-10
申请人： Hyun-Sil Oh , Kitae Park , Soonwook Hwang
发明人： Hyun-Sil Oh , Kitae Park , Soonwook Hwang
IPC分类号： G11C16/08
CPC分类号： G11C16/10 , G11C16/0483
摘要： Provided is a method for programming a nonvolatile memory device. The nonvolatile memory device includes a local word line to divide a memory cell string into a first area including a selected word line and a second area not including the selected word line. In the method, word lines of the first area are driven by a first pass voltage and word lines of the second area driven by a second pass voltage higher than the first pass voltage. A cell transistor corresponding to the local word line is turned off after the first pass voltage and the second pass voltage are applied. The selected word line is driven by a program voltage after the cell transistor is turned off.
摘要翻译：提供了一种用于对非易失性存储器件进行编程的方法。非易失性存储器件包括用于将存储单元串划分成包括所选字线的第一区域和不包括所选字线的第二区域的本地字线。在该方法中，第一区域的字线由第一通过电压和由比第一通过电压高的第二通过电压驱动的第二区域的字线驱动。在施加第一通过电压和第二通过电压之后，对应于本地字线的单元晶体管截止。在单元晶体管截止之后，所选字线由编程电压驱动。

5. 发明授权

US08254181B2 Nonvolatile memory device and programming method 有权
标题翻译：非易失性存储器件和编程方法
公开(公告)号：US08254181B2
公开(公告)日：2012-08-28
申请号：US12581479
申请日：2009-10-19
申请人： Soonwook Hwang , Kitae Park , Jaewook Lee , Han Sung Joo
发明人： Soonwook Hwang , Kitae Park , Jaewook Lee , Han Sung Joo
IPC分类号： G11C16/06 , G11C16/34 , G11C16/24 , G11C16/10
CPC分类号： G11C16/3404 , G11C16/344
摘要： A nonvolatile memory device includes; a memory cell array configured into a plurality of memory blocks, a decoder connected to the plurality of memory blocks via a word line, a page buffer connected to the plurality of memory blocks via a bit line, and control logic configured to define a control voltage applied to at least one of the word line and the bit line during a program/verify operation in accordance with a location of each one of the plurality of memory blocks within the memory cell array.
摘要翻译：非易失性存储装置包括：配置成多个存储器块的存储单元阵列，经由字线连接到多个存储器块的解码器，经由位线连接到多个存储器块的页缓冲器以及被配置为定义控制电压的控制逻辑根据存储单元阵列内的多个存储块中的每一个的位置，在程序/验证操作期间应用于字线和位线中的至少一个。

6. 发明申请

US20100128532A1 NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD 有权
标题翻译：非易失性存储器件和编程方法
公开(公告)号：US20100128532A1
公开(公告)日：2010-05-27
申请号：US12581479
申请日：2009-10-19
申请人： Soonwook HWANG , Kitae PARK , Jaewook LEE , Han Sung JOO
发明人： Soonwook HWANG , Kitae PARK , Jaewook LEE , Han Sung JOO
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3404 , G11C16/344
摘要： A nonvolatile memory device includes; a memory cell array configured into a plurality of memory blocks, a decoder connected to the plurality of memory blocks via a word line, a page buffer connected to the plurality of memory blocks via a bit line, and control logic configured to define a control voltage applied to at least one of the word line and the bit line during a program/verify operation in accordance with a location of each one of the plurality of memory blocks within the memory cell array.
摘要翻译：非易失性存储装置包括：配置成多个存储器块的存储单元阵列，经由字线连接到多个存储器块的解码器，经由位线连接到多个存储器块的页缓冲器以及被配置为定义控制电压的控制逻辑根据存储单元阵列内的多个存储块中的每一个的位置，在程序/验证操作期间应用于字线和位线中的至少一个。

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