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1. 发明授权

US07126154B2 Test structure for a single-sided buried strap DRAM memory cell array 有权
标题翻译：单面埋地带DRAM存储单元阵列的测试结构
公开(公告)号：US07126154B2
公开(公告)日：2006-10-24
申请号：US10933497
申请日：2004-09-03
申请人： Valentine Rosskopf , Susanne Lachenmann , Sibina Sukman-Prähofer , Andreas Felber
发明人： Valentine Rosskopf , Susanne Lachenmann , Sibina Sukman-Prähofer , Andreas Felber
IPC分类号： H01L23/58 , H01L29/10 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/10873 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2029/5002 , H01L22/34 , H01L2924/0002 , Y10S257/905 , Y10S257/908 , H01L2924/00
摘要： A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.
摘要翻译：用于确定基于单面掩埋带概念构造的矩阵状单元阵列中的存储单元的电特性的测试结构具有在两个相邻存储单元中的存储电容器中的内部电极之间的连接该行的有源区为了产生串联电路。第一存储单元中的第一选择晶体管和第一存储电容器以及第二存储单元中的第二选择晶体管和第二存储电容器，第一和第二选择晶体管的有源区不连接在第一和第二选择晶体管之间通过接触式位线。

2. 发明授权

US06917208B2 Method and test structure for determining resistances at a plurality of interconnected resistors in an integrated circuit 失效
标题翻译：用于确定集成电路中的多个互连电阻器的电阻的方法和测试结构
公开(公告)号：US06917208B2
公开(公告)日：2005-07-12
申请号：US10407714
申请日：2003-04-04
申请人： Jürgen Lindolf , Sibina Sukman
发明人： Jürgen Lindolf , Sibina Sukman
IPC分类号： G01R31/28 , G11C29/02 , G01R27/08 , G01R31/02 , G01R31/26
CPC分类号： G11C29/50008 , G01R31/2884 , G11C29/02
摘要： A method for determining resistances at a plurality of interconnected resistors in an integrated circuit and a resistor configuration in which the resistors are interconnected to form a ring structure. Two measurement pads are in each case provided at the nodes between two resistors. The measurement pads can be used for feeding in current and for measuring voltage according to the known four-point measurement method. The effect of the ring structure is that fewer measurement pads are required, in contrast to the customary series circuit of resistors. By way of example, in the case of a ring structure with four resistors, two measurement pads are advantageously saved. The consequently reduced chip area required for the ring structure is advantageous particularly in the case of test circuits, which can be arranged for example in the narrow sawing frame between two chips.
摘要翻译：一种用于确定集成电路中的多个互连电阻器和电阻器配置中的电阻的方法，其中电阻器互连以形成环形结构。在两个电阻之间的节点处提供两个测量垫。测量垫可以根据已知的四点测量方法用于馈送电流和测量电压。与传统的电阻串联电路相比，环形结构的影响是需要更少的测量焊盘。作为示例，在具有四个电阻器的环形结构的情况下，有利地节省了两个测量垫。因此，环形结构所需的减小的芯片面积是有利的，特别是在测试电路的情况下，其可以布置在例如两个芯片之间的窄锯切框架中。

3. 发明申请

US20050051765A1 Test structure for a single-sided buried strap DRAM memory cell array 有权
标题翻译：单面埋地带DRAM存储单元阵列的测试结构
公开(公告)号：US20050051765A1
公开(公告)日：2005-03-10
申请号：US10933497
申请日：2004-09-03
申请人： Valentin Rosskopf , Susanne Lachenmann , Sibina Sukman-Prahofer , Andreas Felber
发明人： Valentin Rosskopf , Susanne Lachenmann , Sibina Sukman-Prahofer , Andreas Felber
IPC分类号： G11C29/00 , G11C29/50 , H01L21/8242 , H01L23/544 , H01L31/0328
CPC分类号： H01L27/10873 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2029/5002 , H01L22/34 , H01L2924/0002 , Y10S257/905 , Y10S257/908 , H01L2924/00
摘要： A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.
摘要翻译：用于确定基于单面掩埋带概念构造的矩阵状单元阵列中的存储单元的电特性的测试结构具有在两个相邻存储单元中的存储电容器中的内部电极之间的连接该行的有源区为了产生串联电路。第一存储单元中的第一选择晶体管和第一存储电容器以及第二存储单元中的第二选择晶体管和第二存储电容器，第一和第二选择晶体管的有源区不连接在第一和第二选择晶体管之间通过接触式位线。

4. 发明申请

US20060138411A1 Semiconductor wafer with a test structure, and method 审中-公开
标题翻译：具有测试结构的半导体晶圆及方法
公开(公告)号：US20060138411A1
公开(公告)日：2006-06-29
申请号：US11293031
申请日：2005-12-02
申请人： Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer , Ramona Winter
发明人： Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer , Ramona Winter
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention proposes a semiconductor wafer with a test structure for detecting parasitic contact structures on the semiconductor wafer, in which a first interconnect plane (A) contains interconnects (1) running parallel to one another and a second interconnect (2) that is arranged between the latter. The two first interconnects (1) are connected by means of contact elements (4) arranged above them, to a third interconnect (3) that runs in a second interconnect plane (B) transverse to the first and second interconnects, and that also crosses the second interconnect (2). If there is a parasitic contact structure (5) formed between the contact elements (4), which has arisen during the lithographic exposure for producing the contact elements (4) on account of constructively interfering diffraction maxima, then this shorts the second interconnect (2) to the third interconnect (3). This results in a leakage current path perpendicular to the substrate surface (10a), the path extending from the second (2) to the third (3) interconnect even in the case of very narrow parasitic contact structures (5). When test needles are placed in contact with the second and third interconnects, an electrical measurement allows the extent of a parasitic contact structure (5) to be detected with a particularly high level of probability.
摘要翻译：本发明提出一种具有用于检测半导体晶片上的寄生接触结构的测试结构的半导体晶片，其中第一互连平面（A）包含彼此平行延伸的互连（1）和布置在后者。两个第一互连（1）通过布置在其上方的接触元件（4）连接到在横向于第一和第二互连的第二互连平面（B）中延伸的第三互连（3），并且还穿过第二互连（2）。如果在由于构造上的干涉衍射最大值产生接触元件（4）的光刻曝光期间产生的接触元件（4）之间形成寄生接触结构（5），则这将使第二互连（2 ）到第三互连（3）。这导致即使在非常窄的寄生接触结构（5）的情况下，垂直于衬底表面（10a）的漏电流路径也是从第二（2）到第三（3）互连的路径。当测试针与第二和第三互连件接触时，电测量允许以特别高的概率来检测寄生接触结构（5）的程度。

5. 发明授权

US07372072B2 Semiconductor wafer with test structure 有权
标题翻译：具有测试结构的半导体晶圆
公开(公告)号：US07372072B2
公开(公告)日：2008-05-13
申请号：US11304074
申请日：2005-12-15
申请人： Ramona Winter , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
发明人： Ramona Winter , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
IPC分类号： H01L21/301
CPC分类号： H01L22/32 , H01L22/34
摘要： The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in each case contain an integrated circuit (100) and which are in each case arranged between respective adjacent first sawing regions (201-211) and respective adjacent second sawing regions (301-311), and at least one test structure region arranged in the first sawing regions (201-211) and the second sawing regions (301-311) with test structures formed therein for checking electrical parameters of semiconductor elements. Connection contacts (51-54) connected to the test structures are provided in the test structure region, which connection contacts form a first row (R1) and a second row (R2), which in each case run in a longitudinal direction (L) and are offset relative to one another in the longitudinal direction (L) and transversely with respect to the longitudinal direction (L).
摘要翻译：本发明涉及一种半导体晶片（1），具有在第一方向（X）上彼此平行延伸的多个第一锯切区域（201-211）和平行于一个方向的多个第二锯切区域（301-311）另一个在第二方向（Y）上，具有有用的区域（10），每个区域包含集成电路（100），并且各自在各自的情况下布置在相邻的第一锯切区域（201-211）和相应的相邻的第二锯切区域（301-311）以及布置在第一锯切区域（201-211）和第二锯切区域（301-311）中的至少一个测试结构区域，其中形成有用于检查半导体元件的电参数的测试结构。连接到测试结构的连接触点（51-54）设置在测试结构区域中，该连接触点形成第一排（R 1）和第二排（R 2），其在每种情况下沿纵向延伸 L）并且在纵向方向（L）上相对于彼此偏移并且相对于纵向方向（L）横向偏移。

6. 发明授权

US07205567B2 Semiconductor product having a semiconductor substrate and a test structure and method 失效
标题翻译：具有半导体衬底和测试结构和方法的半导体产品
公开(公告)号：US07205567B2
公开(公告)日：2007-04-17
申请号：US11336384
申请日：2006-01-20
申请人： Andreas Felber , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
发明人： Andreas Felber , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to determine the nonreactive resistance of dopant diffusion regions, the so-called “buried straps”, without the measurement result being corrupted by the nonreactive resistance of a transistor channel. In accordance with one embodiment of the invention having a plurality of electrical connections of the capacitor electrode, static currents can also be conducted through a buried strap and the capacitor electrode. Embodiments are disclosed that make it possible to perform at novel test structures of a semiconductor wafer electrical resistance measurements, which cannot be carried out at memory cells of a memory cell array themselves.
摘要翻译：具有测试结构的半导体产品，其中公开了通过具有互连的掺杂剂扩散区将接触连接短路到与沟槽电容器的内部电容器电极连接的晶体管的源极/漏极区域。公开了用于进行电气测量的方法，以确定掺杂剂扩散区域的非反应电阻，即所谓的“掩埋带”，而测量结果不被晶体管通道的非反应电阻破坏。根据具有电容器电极的多个电连接的本发明的一个实施例，静电流也可以通过掩埋带和电容器电极进行。公开了使得可以在半导体晶片电阻测量的新颖测试结构下执行，其不能在存储器单元阵列本身的存储器单元处执行。

7. 发明申请

US20060175647A1 Semiconductor product having a semiconductor substrate and a test structure and method 失效
标题翻译：具有半导体衬底和测试结构和方法的半导体产品
公开(公告)号：US20060175647A1
公开(公告)日：2006-08-10
申请号：US11336384
申请日：2006-01-20
申请人： Andreas Felber , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
发明人： Andreas Felber , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
IPC分类号： H01L29/94
CPC分类号： H01L22/34 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to determine the nonreactive resistance of dopant diffusion regions, the so-called “buried straps”, without the measurement result being corrupted by the nonreactive resistance of a transistor channel. In accordance with one embodiment of the invention having a plurality of electrical connections of the capacitor electrode, static currents can also be conducted through a buried strap and the capacitor electrode. Embodiments are disclosed that make it possible to perform at novel test structures of a semiconductor wafer electrical resistance measurements, which cannot be carried out at memory cells of a memory cell array themselves.
摘要翻译：具有测试结构的半导体产品，其中公开了通过具有互连的掺杂剂扩散区将接触连接短路到与沟槽电容器的内部电容器电极连接的晶体管的源极/漏极区域。公开了用于进行电气测量的方法，以确定掺杂剂扩散区域的非反应电阻，即所谓的“掩埋带”，而测量结果不被晶体管通道的非反应电阻破坏。根据具有电容器电极的多个电连接的本发明的一个实施例，静电流也可以通过掩埋带和电容器电极进行。公开了使得可以在半导体晶片电阻测量的新颖测试结构下执行，其不能在存储器单元阵列本身的存储器单元处执行。

8. 发明申请

US20060157702A1 Kerf with improved fill routine 审中-公开
标题翻译：改善填充程序的Kerf
公开(公告)号：US20060157702A1
公开(公告)日：2006-07-20
申请号：US11334754
申请日：2006-01-19
申请人： Sibina Sukman-Prahofer , Susanne Lachenmann , Valentin Rosskopf , Ramona Winter
发明人： Sibina Sukman-Prahofer , Susanne Lachenmann , Valentin Rosskopf , Ramona Winter
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34
摘要： A semiconductor disk which exhibits chip areas arranged next to one another and separated from one another by a kerf. The chip areas in each case exhibit a multiplicity of similar device patterns, such that at least one fill area with fill patterns is arranged in the kerf, and the fill patterns in the kerf and the device patterns in the chip areas are essentially similarly constructed.
摘要翻译：一种半导体盘，其显示彼此相邻布置并通过切口彼此分离的芯片区域。在每种情况下，芯片区域表现出多种类似的装置图案，使得具有填充图案的至少一个填充区域被布置在切口中，切屑区域中的填充图案和芯片区域中的装置图案基本上类似地构造。

9. 发明申请

US20060157700A1 Semiconductor wafer with test structure 有权
标题翻译：具有测试结构的半导体晶圆
公开(公告)号：US20060157700A1
公开(公告)日：2006-07-20
申请号：US11304074
申请日：2005-12-15
申请人： Ramona Winter , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
发明人： Ramona Winter , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/32 , H01L22/34
摘要： The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in each case contain an integrated circuit (100) and which are in each case arranged between respective adjacent first sawing regions (201-211) and respective adjacent second sawing regions (301-311), and at least one test structure region arranged in the first sawing regions (201-211) and the second sawing regions (301-311) with test structures formed therein for checking electrical parameters of semiconductor elements. Connection contacts (51-54) connected to the test structures are provided in the test structure region, which connection contacts form a first row (R1) and a second row (R2), which in each case run in a longitudinal direction (L) and are offset relative to one another in the longitudinal direction (L) and transversely with respect to the longitudinal direction (L).
摘要翻译：本发明涉及一种半导体晶片（1），具有在第一方向（X）上彼此平行延伸的多个第一锯切区域（201-211）和平行于一个方向的多个第二锯切区域（301-311）另一个在第二方向（Y）上，具有有用的区域（10），每个区域包含集成电路（100），并且各自在各自的情况下布置在相邻的第一锯切区域（201-211）和相应的相邻的第二锯切区域（301-311）以及布置在第一锯切区域（201-211）和第二锯切区域（301-311）中的至少一个测试结构区域，其中形成有用于检查半导体元件的电参数的测试结构。连接到测试结构的连接触点（51-54）设置在测试结构区域中，该连接触点形成第一排（R 1）和第二排（R 2），其在每种情况下沿纵向延伸 L）并且在纵向方向（L）上相对于彼此偏移并且相对于纵向方向（L）横向偏移。

10. 发明授权

US06856562B2 Test structure for measuring a junction resistance in a DRAM memory cell array 失效
标题翻译：用于测量DRAM存储单元阵列中的结电阻的测试结构
公开(公告)号：US06856562B2
公开(公告)日：2005-02-15
申请号：US10659843
申请日：2003-09-11
申请人： Susanne Lachenmann , Valentin Rosskopf , Andreas Felber , Sibina Sukman
发明人： Susanne Lachenmann , Valentin Rosskopf , Andreas Felber , Sibina Sukman
IPC分类号： G11C29/02 , G11C29/50 , H01L21/8242 , H01L23/544 , G11C7/00
CPC分类号： H01L27/10867 , G11C11/401 , G11C29/02 , G11C29/50 , G11C29/50008 , H01L22/34 , H01L2924/3011
摘要： A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array where the active regions of the selection transistors are in rows in a first direction and the storage capacitors are in rows in a second direction running perpendicular to the first direction. The conducting junctions between the active regions of the selection transistors and the storage capacitors are formed at overlapping areas of the mutually perpendicular rows each in a single edge region of the overlapping area in the first direction. The active regions of the selection transistors and/or the storage capacitors are connected by tunnel structures or bridge structures in the second direction in the region adjoining the junction to be measured between the active region of the selection transistor and the storage capacitor. This achieves a low-impedance connection to the junction to be measured.
摘要翻译：一种用于确定选择晶体管的有源区域在第一方向上成行并且存储电容器的矩阵型单元阵列中的选择晶体管的有源区域和存储电容器之间的导电结的电阻的测试结构，在垂直于第一方向的第二方向上行。选择晶体管的有源区域和存储电容器之间的导体结形成在相互垂直的行的重叠区域中，每个重叠区域在重叠区域的第一方向的单个边缘区域中。选择晶体管和/或存储电容器的有源区域在与选择晶体管的有源区域和存储电容器之间的待测量结的邻接区域中的第二方向上的隧道结构或桥接结构连接。这实现了到要测量的结的低阻抗连接。

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