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1. 发明申请

US20060138411A1 Semiconductor wafer with a test structure, and method 审中-公开
标题翻译：具有测试结构的半导体晶圆及方法
公开(公告)号：US20060138411A1
公开(公告)日：2006-06-29
申请号：US11293031
申请日：2005-12-02
申请人： Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer , Ramona Winter
发明人： Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer , Ramona Winter
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention proposes a semiconductor wafer with a test structure for detecting parasitic contact structures on the semiconductor wafer, in which a first interconnect plane (A) contains interconnects (1) running parallel to one another and a second interconnect (2) that is arranged between the latter. The two first interconnects (1) are connected by means of contact elements (4) arranged above them, to a third interconnect (3) that runs in a second interconnect plane (B) transverse to the first and second interconnects, and that also crosses the second interconnect (2). If there is a parasitic contact structure (5) formed between the contact elements (4), which has arisen during the lithographic exposure for producing the contact elements (4) on account of constructively interfering diffraction maxima, then this shorts the second interconnect (2) to the third interconnect (3). This results in a leakage current path perpendicular to the substrate surface (10a), the path extending from the second (2) to the third (3) interconnect even in the case of very narrow parasitic contact structures (5). When test needles are placed in contact with the second and third interconnects, an electrical measurement allows the extent of a parasitic contact structure (5) to be detected with a particularly high level of probability.
摘要翻译：本发明提出一种具有用于检测半导体晶片上的寄生接触结构的测试结构的半导体晶片，其中第一互连平面（A）包含彼此平行延伸的互连（1）和布置在后者。两个第一互连（1）通过布置在其上方的接触元件（4）连接到在横向于第一和第二互连的第二互连平面（B）中延伸的第三互连（3），并且还穿过第二互连（2）。如果在由于构造上的干涉衍射最大值产生接触元件（4）的光刻曝光期间产生的接触元件（4）之间形成寄生接触结构（5），则这将使第二互连（2 ）到第三互连（3）。这导致即使在非常窄的寄生接触结构（5）的情况下，垂直于衬底表面（10a）的漏电流路径也是从第二（2）到第三（3）互连的路径。当测试针与第二和第三互连件接触时，电测量允许以特别高的概率来检测寄生接触结构（5）的程度。

2. 发明授权

US07372072B2 Semiconductor wafer with test structure 有权
标题翻译：具有测试结构的半导体晶圆
公开(公告)号：US07372072B2
公开(公告)日：2008-05-13
申请号：US11304074
申请日：2005-12-15
申请人： Ramona Winter , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
发明人： Ramona Winter , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
IPC分类号： H01L21/301
CPC分类号： H01L22/32 , H01L22/34
摘要： The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in each case contain an integrated circuit (100) and which are in each case arranged between respective adjacent first sawing regions (201-211) and respective adjacent second sawing regions (301-311), and at least one test structure region arranged in the first sawing regions (201-211) and the second sawing regions (301-311) with test structures formed therein for checking electrical parameters of semiconductor elements. Connection contacts (51-54) connected to the test structures are provided in the test structure region, which connection contacts form a first row (R1) and a second row (R2), which in each case run in a longitudinal direction (L) and are offset relative to one another in the longitudinal direction (L) and transversely with respect to the longitudinal direction (L).
摘要翻译：本发明涉及一种半导体晶片（1），具有在第一方向（X）上彼此平行延伸的多个第一锯切区域（201-211）和平行于一个方向的多个第二锯切区域（301-311）另一个在第二方向（Y）上，具有有用的区域（10），每个区域包含集成电路（100），并且各自在各自的情况下布置在相邻的第一锯切区域（201-211）和相应的相邻的第二锯切区域（301-311）以及布置在第一锯切区域（201-211）和第二锯切区域（301-311）中的至少一个测试结构区域，其中形成有用于检查半导体元件的电参数的测试结构。连接到测试结构的连接触点（51-54）设置在测试结构区域中，该连接触点形成第一排（R 1）和第二排（R 2），其在每种情况下沿纵向延伸 L）并且在纵向方向（L）上相对于彼此偏移并且相对于纵向方向（L）横向偏移。

3. 发明申请

US20060157700A1 Semiconductor wafer with test structure 有权
标题翻译：具有测试结构的半导体晶圆
公开(公告)号：US20060157700A1
公开(公告)日：2006-07-20
申请号：US11304074
申请日：2005-12-15
申请人： Ramona Winter , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
发明人： Ramona Winter , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/32 , H01L22/34
摘要： The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in each case contain an integrated circuit (100) and which are in each case arranged between respective adjacent first sawing regions (201-211) and respective adjacent second sawing regions (301-311), and at least one test structure region arranged in the first sawing regions (201-211) and the second sawing regions (301-311) with test structures formed therein for checking electrical parameters of semiconductor elements. Connection contacts (51-54) connected to the test structures are provided in the test structure region, which connection contacts form a first row (R1) and a second row (R2), which in each case run in a longitudinal direction (L) and are offset relative to one another in the longitudinal direction (L) and transversely with respect to the longitudinal direction (L).
摘要翻译：本发明涉及一种半导体晶片（1），具有在第一方向（X）上彼此平行延伸的多个第一锯切区域（201-211）和平行于一个方向的多个第二锯切区域（301-311）另一个在第二方向（Y）上，具有有用的区域（10），每个区域包含集成电路（100），并且各自在各自的情况下布置在相邻的第一锯切区域（201-211）和相应的相邻的第二锯切区域（301-311）以及布置在第一锯切区域（201-211）和第二锯切区域（301-311）中的至少一个测试结构区域，其中形成有用于检查半导体元件的电参数的测试结构。连接到测试结构的连接触点（51-54）设置在测试结构区域中，该连接触点形成第一排（R 1）和第二排（R 2），其在每种情况下沿纵向延伸 L）并且在纵向方向（L）上相对于彼此偏移并且相对于纵向方向（L）横向偏移。

4. 发明申请

US20060157702A1 Kerf with improved fill routine 审中-公开
标题翻译：改善填充程序的Kerf
公开(公告)号：US20060157702A1
公开(公告)日：2006-07-20
申请号：US11334754
申请日：2006-01-19
申请人： Sibina Sukman-Prahofer , Susanne Lachenmann , Valentin Rosskopf , Ramona Winter
发明人： Sibina Sukman-Prahofer , Susanne Lachenmann , Valentin Rosskopf , Ramona Winter
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34
摘要： A semiconductor disk which exhibits chip areas arranged next to one another and separated from one another by a kerf. The chip areas in each case exhibit a multiplicity of similar device patterns, such that at least one fill area with fill patterns is arranged in the kerf, and the fill patterns in the kerf and the device patterns in the chip areas are essentially similarly constructed.
摘要翻译：一种半导体盘，其显示彼此相邻布置并通过切口彼此分离的芯片区域。在每种情况下，芯片区域表现出多种类似的装置图案，使得具有填充图案的至少一个填充区域被布置在切口中，切屑区域中的填充图案和芯片区域中的装置图案基本上类似地构造。

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