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1. 发明授权

US08477146B2 Processing rasterized data 有权
公开(公告)号：US08477146B2
公开(公告)日：2013-07-02
申请号：US12511238
申请日：2009-07-29
申请人： Shuhua Xiang , Li Sha , Ching-Han Tsai
发明人： Shuhua Xiang , Li Sha , Ching-Han Tsai
IPC分类号： G06T9/00 , G06F12/02 , G06F12/10
CPC分类号： H04N19/423 , H04N19/433 , H04N19/44 , H04N19/61
摘要： Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

2. 发明授权

US07085320B2 Multiple format video compression 失效
标题翻译：多格式视频压缩
公开(公告)号：US07085320B2
公开(公告)日：2006-08-01
申请号：US09953053
申请日：2001-09-14
申请人： He Ouyang , Li Sha , Shuhua Xiang , Yaojun Luo , Weimin Zeng , Jun Ding
发明人： He Ouyang , Li Sha , Shuhua Xiang , Yaojun Luo , Weimin Zeng , Jun Ding
IPC分类号： H04B7/12
CPC分类号： H04N21/440218 , H04N19/12 , H04N19/40 , H04N19/42 , H04N19/61
摘要： A video compression scheme enables the user to select one of many video compression formats, including the widely-used standard video formats such as MPEG-1, MPEG-2, MPEG-4 and H.263. In one embodiment, the scheme is implemented as a hardware-software combination, with the hardware portion, preferably implemented as an ASIC chip, performing the core compression and the software portion dealing with the detailed formatting. In another embodiment, a 32-bit aligned transitional data format is used.
摘要翻译：视频压缩方案使得用户能够选择许多视频压缩格式之一，包括广泛使用的标准视频格式，如MPEG-1，MPEG-2，MPEG-4和H.263。在一个实施例中，该方案被实现为硬件 - 软件组合，硬件部分优选地实现为ASIC芯片，执行核心压缩以及处理详细格式化的软件部分。在另一个实施例中，使用32位对齐的过渡数据格式。

3. 发明授权

US06996702B2 Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention 失效
标题翻译：处理单元具有交叉耦合的ALU /累加器和输入数据反馈结构，包括恒定发生器和旁路以减少内存争用
公开(公告)号：US06996702B2
公开(公告)日：2006-02-07
申请号：US10209109
申请日：2002-07-30
申请人： Shuhua Xiang , Li Sha , Ping Zhu , Hongjun Yuan , Wei Ni
发明人： Shuhua Xiang , Li Sha , Ping Zhu , Hongjun Yuan , Wei Ni
IPC分类号： G06F9/34
CPC分类号： G06F9/3867 , G06F7/57 , G06F9/3824 , G06F9/3826 , G06F9/3885
摘要： A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.
摘要翻译：处理系统包括算术逻辑单元（ALU）子系统，其允许与先前指令相关联的数据被保留以用于下一个指令或后续指令，而不必使用中间寄存器重新加载该值。 ALU子系统包括与一对蓄能器通信地交叉耦合的一对ALU。处理系统还包括耦合到ALU子系统以与存储器争用预测一起使用的数据选择器。数据选择器包括恒定发生器，其控制与旁路元件中的先前指令相关联的数据的存储，以及选择器，用于在数据总线元件的数据和存储在旁路元件中的数据之间进行选择。

4. 发明申请

US20050207488A1 DCT/IDCT WITH MINIMUM MULTIPLICATION 失效
标题翻译：具有最小化的DCT / IDCT
公开(公告)号：US20050207488A1
公开(公告)日：2005-09-22
申请号：US09924140
申请日：2001-08-07
申请人： He Ouyang , Li Sha , Shuhua Xiang , Ping Zhu , Yaojun Luo
发明人： He Ouyang , Li Sha , Shuhua Xiang , Ping Zhu , Yaojun Luo
IPC分类号： G06F17/14 , H04N7/12 , H04N7/26 , H04N7/50
CPC分类号： G06F17/147 , H04N19/423 , H04N19/43 , H04N19/61
摘要： A method, apparatus, computer medium, and other embodiments for discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) of image signals are described. A DCT/IDCT module includes a plurality of different cores. One embodiment of a core includes two sets of lookup tables to provide multiplication and add operations for the DCT and IDCT functions. Another embodiment of a core include one set of lookup tables, while another embodiment of a core includes no lookup table. The DCT/IDCT module provides forward DCT and IDCT functionality without the use of additional multipliers.
摘要翻译：描述了用于图像信号的离散余弦变换和逆离散余弦变换（DCT / IDCT）的方法，装置，计算机介质和其他实施例。 DCT / IDCT模块包括多个不同的核。核心的一个实施例包括两组查找表，用于为DCT和IDCT功能提供乘法和加法运算。核心的另一实施例包括一组查找表，而核心的另一实施例不包括查找表。 DCT / IDCT模块提供前向DCT和IDCT功能，而不需要使用额外的乘法器。

5. 发明授权

US08878870B1 Graphic processing techniques and configurations 有权
标题翻译：图形处理技术和配置
公开(公告)号：US08878870B1
公开(公告)日：2014-11-04
申请号：US12533554
申请日：2009-07-31
申请人： Satish Kumar Vutukuri , Haohong Wang , Li Sha , Tao Xie , Ching-Han Tsai , Tzun-Wei Lee , Leung Chung Lai , Shuhua Xiang
发明人： Satish Kumar Vutukuri , Haohong Wang , Li Sha , Tao Xie , Ching-Han Tsai , Tzun-Wei Lee , Leung Chung Lai , Shuhua Xiang
IPC分类号： G09G5/00 , G09G5/377 , G06T3/40 , G06T15/00 , G06T15/40 , G06T15/50
CPC分类号： G09G5/377 , G06F3/14 , G09G5/14 , G09G2310/0229 , G09G2340/125 , G09G2350/00
摘要： Embodiments of the present invention provide graphic processing techniques and configurations including an apparatus comprising a storage medium having stored therein a table comprising information about respective positions and sizes of a number of rectangular blocks, the rectangular blocks to substantially form at least one plane having an arbitrary shape object, and at least one overlay engine operatively coupled with the table and associated with the at least one plane to request the information about the respective positions and the sizes of the number of rectangular blocks to provide graphics overlay of the arbitrary shape object. Other embodiments may be described and/or claimed.
摘要翻译：本发明的实施例提供了图形处理技术和配置，其包括包括存储介质的设备，其中存储有包括关于多个矩形块的相应位置和大小的信息的表格，矩形块基本上形成至少一个具有任意以及至少一个覆盖引擎，其可操作地与所述工作台耦合并与所述至少一个平面相关联，以请求关于矩形块的数量的相应位置和尺寸的信息以提供所述任意形状对象的图形叠加。可以描述和/或要求保护其他实施例。

6. 发明授权

US08645400B1 Flexible bit field search method 有权
标题翻译：灵活的位字段搜索方法
公开(公告)号：US08645400B1
公开(公告)日：2014-02-04
申请号：US12512902
申请日：2009-07-30
申请人： Shuhua Xiang , Venkata Narayana Pinnamaraju Durga
发明人： Shuhua Xiang , Venkata Narayana Pinnamaraju Durga
IPC分类号： G06F7/00
CPC分类号： G06F17/30699 , G06F7/02 , G06F2207/025
摘要： A method and apparatus uses a section filter to perform a filtering operation, such as a match, do not match, within range, or without range filtering operation, on bitstream data in accordance with a rule. The filtering operation may begin at any bit location in the bitstream data and end at any location in the bitstream data. The result of the filtering operation is compared to a value determined by the rule, or if further rules are to be employed, the result is transmitted to a further section filter which performs a further filtering operation on the bitstream data. As many section filters may be linked in this way as the number of rules to be employed. When the section filter corresponding to the last rule to be employed has performed its filtering operation, all results are compared to values determined by the rules employed to determine which data to extract from the bitstream data.
摘要翻译：根据规则，方法和装置使用截面滤波器对比特流数据执行滤波操作，例如匹配，在范围内或不带范围滤波操作中不匹配。滤波操作可以从比特流数据中的任何比特位置开始并在比特流数据中的任何位置结束。将滤波操作的结果与由规则确定的值进行比较，或者如果要采用进一步的规则，则将结果发送到对比特流数据执行进一步滤波操作的另外的部分滤波器。许多分段过滤器可以以这种方式被链接为要使用的规则的数量。当与要使用的最后一个规则相对应的部分过滤器已经执行了其过滤操作时，将所有结果与由用于确定从比特流数据中提取哪些数据的规则确定的值进行比较。

7. 发明申请

US20100026697A1 PROCESSING RASTERIZED DATA 有权
标题翻译：处理RASTERIZED数据
公开(公告)号：US20100026697A1
公开(公告)日：2010-02-04
申请号：US12511238
申请日：2009-07-29
申请人： Shuhua XIANG , Li SHA , Ching-Han TSAI
发明人： Shuhua XIANG , Li SHA , Ching-Han TSAI
IPC分类号： G06F12/00
CPC分类号： H04N19/423 , H04N19/433 , H04N19/44 , H04N19/61
摘要： Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.
摘要翻译：描述了与处理光栅化数据相关联的设备，方法和其他实施例。在一个实施例中，一种装置包括用于将压缩图像的光栅化像素数据的线转换成多个二维数据块的转换逻辑。光栅化像素数据的行存储在连续的存储单元中。每个数据块被存储在连续的存储单元中。该装置包括用于至少部分地基于二维数据块至少部分地解压缩压缩图像的解压缩逻辑。

8. 发明申请

US20080222332A1 COMBINED ENGINE FOR VIDEO AND GRAPHICS PROCESSING 失效
标题翻译：用于视频和图形处理的组合发动机
公开(公告)号：US20080222332A1
公开(公告)日：2008-09-11
申请号：US12123282
申请日：2008-05-19
申请人： Enoch Y. LEE , Li SHA , Shuhua XIANG
发明人： Enoch Y. LEE , Li SHA , Shuhua XIANG
IPC分类号： G06F13/18
CPC分类号： G06T1/20 , G06F3/14 , G09G5/001 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/10 , G09G2340/125 , G09G2360/06 , G09G2360/10
摘要： The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.
摘要翻译：该系统包括仲裁器，组合引擎，帧缓冲器和显示处理单元。仲裁器提供三个输入通道：第一个图形通道，第二个视频通道和第三个处理器通道。仲裁器在发送到系统的视频和图形以及处理器请求之间执行优先级排序和仲裁。仲裁器具有耦合到组合引擎的三个输出端口。组合引擎是能够处理视频数据或图形数据的硬件引擎。组合引擎的输出被提供给帧缓冲器以用于存储像素数据。帧缓冲器的输出耦合到显示处理单元，该显示处理单元呈现用于显示的像素数据。

9. 发明申请

US20060130149A1 Digital rights management microprocessing architecture 审中-公开
标题翻译：数字版权管理微处理架构
公开(公告)号：US20060130149A1
公开(公告)日：2006-06-15
申请号：US11187358
申请日：2005-07-21
申请人： Shuhua Xiang
发明人： Shuhua Xiang
IPC分类号： H04N7/16
CPC分类号： H04N21/4405 , G06F21/10 , G06F21/71 , H04N21/42692
摘要： A system rights management system can process a multi-media data stream. In an embodiment, the system includes digital rights management (DRM) processing modules, shared first in first out (FIFO) buffers, and a cross-bar switch for channeling data between the DRM modules and the shared FIFO buffers. In another embodiment, the system includes an embedded processor, allowing DRM processing tasks to be performed using a dedicated processor rather than tying up the resources of a general CPU.
摘要翻译：系统权限管理系统可以处理多媒体数据流。在一个实施例中，系统包括数字权限管理（DRM）处理模块，先进先出（FIFO）缓冲器，以及用于在DRM模块和共享FIFO缓冲器之间引导数据的交叉开关。在另一个实施例中，系统包括嵌入式处理器，允许使用专用处理器执行DRM处理任务，而不是捆绑一般CPU的资源。

10. 发明申请

US20050228970A1 PROCESSING UNIT WITH CROSS-COUPLED ALUS/ACCUMULATORS AND INPUT DATA FEEDBACK STRUCTURE INCLUDING CONSTANT GENERATOR AND BYPASS TO REDUCE MEMORY CONTENTION 失效
标题翻译：具有交叉耦合ALUS /累加器的加工单元和输入数据反馈结构，包括恒定发电机和旁路以减少存储器内容
公开(公告)号：US20050228970A1
公开(公告)日：2005-10-13
申请号：US10209109
申请日：2002-07-30
申请人： Shuhua Xiang , Li Sha , Ping Zhu , Hongjun Yuan , Wei Ni
发明人： Shuhua Xiang , Li Sha , Ping Zhu , Hongjun Yuan , Wei Ni
IPC分类号： G06F7/57 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3867 , G06F7/57 , G06F9/3824 , G06F9/3826 , G06F9/3885
摘要： A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.
摘要翻译：处理系统包括算术逻辑单元（ALU）子系统，其允许与先前指令相关联的数据被保留以用于下一个指令或后续指令，而不必使用中间寄存器重新加载该值。 ALU子系统包括与一对蓄能器通信地交叉耦合的一对ALU。处理系统还包括耦合到ALU子系统以与存储器争用预测一起使用的数据选择器。数据选择器包括恒定发生器，其控制与旁路元件中的先前指令相关联的数据的存储，以及选择器，用于在数据总线元件的数据和存储在旁路元件中的数据之间进行选择。

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