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1. 发明授权

US06538523B2 Multi-channel pulse width modulation apparatus and down counter 有权
标题翻译：多通道脉宽调制装置和倒计时器
公开(公告)号：US06538523B2
公开(公告)日：2003-03-25
申请号：US09741104
申请日：2000-12-21
申请人： Yukio Sugita , Shinjiro Toyoda , Takashi Toyoda
发明人： Yukio Sugita , Shinjiro Toyoda , Takashi Toyoda
IPC分类号： H03K708
CPC分类号： G06F1/025 , H03K7/08 , H04N1/40031
摘要： When a PWM signal is generated by PWM generators which are provided for the number of channels, each PWM generator outputs the PWM start schedule data showing the timing of startup of the PWM signal to the CPU. When the number of PWM signals which start at substantially the same time exceeds a predetermined number on the basis of the PWM start schedule data, the CPU outputs delay setting data with respect to a channel corresponding to a portion exceeding the predetermined number to the PWM generator as the one showing that the generation of the PWM signal is to be delayed. The PWM generator delays the PWM signal, when the delay setting data shows a delay. As a result, a multi-channel pulse width modulation apparatus which can prevent a decrease in the operational reliability due to simultaneous start of the pulse width modulation signals can be provided.
摘要翻译：当PWM信号由通道数量的PWM发生器产生时，每个PWM发生器将表示PWM信号启动定时的PWM启动调度数据输出到CPU。当基于PWM启动调度数据基本相同的时间开始的PWM信号的数量超过预定数量时，CPU将关于与超过预定数量的部分相对应的通道的延迟设置数据输出到PWM发生器作为显示PWM信号的产生被延迟的那个。当延迟设置数据显示延迟时，PWM发生器会延迟PWM信号。结果，可以提供可以防止由于脉冲宽度调制信号的同时启动而引起的操作可靠性降低的多通道脉宽调制装置。

2. 发明授权

US5572447A Coordinate difference calculating device 失效
标题翻译：坐标差计算装置
公开(公告)号：US5572447A
公开(公告)日：1996-11-05
申请号：US160800
申请日：1993-12-03
申请人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： G06F7/544 , G06F17/50 , G01N15/02 , G01B21/16
CPC分类号： G06F7/544 , G06F19/704 , G06F19/701
摘要： A device for calculating differences includes a difference circuit for generating difference signals .DELTA.x.sub.j =x.sub.j -x.sub.i, .DELTA.y.sub.j =y.sub.j -y.sub.i, and .DELTA.z.sub.j =z.sub.j -z.sub.i between coordinates of i having (x.sub.i, y.sub.i, z.sub.i) coordinate signals and coordinates of j having (x.sub.j, y.sub.j, z.sub.j) coordinate signals in an orthogonal coordinate system. The difference circuit includes an x-axis circuit, responsive to the x.sub.i and x.sub.j signals having a first circuit for receiving the x.sub.i coordinate signal and the x.sub.j coordinate signal and generating the .DELTA.x.sub.j ; a comparison circuit for comparing the x.sub.i and x.sub.j signals and determining whether the .DELTA.x.sub.j is less than a first set value -L.sub.x /2 corresponding to a length of a side of a virtual rectangular parallelepiped or greater than a second set value L.sub.x /2 corresponding to the length of the side of the virtual rectangular parallelepiped, L.sub.x being a value indicating the length of an elongated side in the x-axis direction of the virtual rectangular parallelepiped; an adder circuit for receiving the L.sub.x and .DELTA.x.sub.j and adding the L.sub.x to .DELTA.x.sub.j when .DELTA.x.sub.j is less than -L.sub.x /2; and a subtraction circuit for receiving the L.sub.x and .DELTA.x.sub.j and subtracting L.sub.x from .DELTA.x.sub.j when .DELTA.x.sub.j is greater than L.sub.x /2. The difference circuit includes y-axis and z-axis circuits similar to the x-axis circuit.
摘要翻译：用于计算差分的装置包括用于产生具有（xi，yi，zi）坐标信号和坐标的坐标之间的差分信号DELTA xj = xj-xi，DELTA yj = yj-yi和DELTA zj = zj-zi的差分电路具有在正交坐标系中的（xj，yj，zj）坐标信号的j。差分电路包括x轴电路，响应于具有用于接收xi坐标信号和xj坐标信号并产生DELTA xj的第一电路的xi和xj信号; 用于比较xi和xj信号并确定DELTA xj是否小于对应于虚拟长方体的一侧的长度或大于第二设定值Lx / 2的对应的第一设定值-Lx / 2的比较电路到虚拟长方体的一侧的长度，Lx是表示虚拟长方体的x轴方向上的细长侧的长度的值; 加法器电路，用于当DELTA xj小于-Lx / 2时，接收Lx和DELTA xj并将Lx加到DELTA xj; 以及减法电路，用于当DELTA xj大于Lx / 2时，从DELTA xj接收Lx和DELTA xj并从DELTA xj中减去Lx。差分电路包括类似于x轴电路的y轴和z轴电路。

3. 发明授权

US5251270A Matrix calculating circuit 失效
标题翻译：矩阵计算电路
公开(公告)号：US5251270A
公开(公告)日：1993-10-05
申请号：US17440
申请日：1993-02-12
申请人： Shinjiro Toyoda
发明人： Shinjiro Toyoda
IPC分类号： H04N5/359 , H04N5/369 , G06K9/00
CPC分类号： H04N5/3692 , H04N5/3577 , H04N5/3653
摘要： A matrix calculating circuit for calculating with respect to a matrix in which all diagonal elements are equal to one another and the remaining elements are equal to one another. The matrix calculating circuit includes a register for successively latching "n" items of data that are time-sequentially inputted thereto, a delay circuit for delaying the data supplied from the register by "n" clocks, a total-sum calculating unit for calculating a total sum of the "n" items of data supplied from the register, a data latch for latching a value of the total-sum calculating unit, and an adder for adding output data of the delay circuit to output data of the data latch. The "n" items of data to be latched by the register may be supplied from an output portion of an image sensor, to remove the influence due to the crosstalk.
摘要翻译：一种矩阵计算电路，用于相对于其中所有对角元素彼此相等并且其余元素彼此相等的矩阵进行计算。矩阵计算电路包括用于连续地锁存“n”个数据的时间顺序地输入的寄存器，用于将由寄存器提供的数据延迟“n”个时钟的延迟电路，总和计算单元，用于计算从寄存器提供的“n”项数据的总和，用于锁存总和计算单元的值的数据锁存器和用于将延迟电路的输出数据添加到数据锁存器的输出数据的加法器。由寄存器锁存的“n”项数据可以从图像传感器的输出部分提供，以消除由于串扰引起的影响。

4. 发明授权

US6073155A Floating-point accumulator 失效
标题翻译：浮点累加器
公开(公告)号：US6073155A
公开(公告)日：2000-06-06
申请号：US901671
申请日：1997-07-28
申请人： Shinjiro Inabata , So Yamada , Shinjiro Toyoda , Nobuaki Miyakawa
发明人： Shinjiro Inabata , So Yamada , Shinjiro Toyoda , Nobuaki Miyakawa
IPC分类号： G06F7/485 , G06F7/50 , G06F17/10 , G06F7/38
CPC分类号： G06F7/485
摘要： To obtain the sufficiently precise result of floating-point accumulation even if the quantity of computation is enormous, a floating-point accumulator according to the present invention is constituted as follows:When two floating-point data are stored in any of shift registers, the two data are respectively output to BUS0 and BUS1 via one connected to the shift register of buffers. The two output data are input to an adder via BUS0 and BUS1 and output as added result data after adding the floating-point numbers. The above added result data is returned to each input of the shift registers via BUSW and a multiplexer and written into the shift register corresponding to the addition of the higher level by one of the shift register holding floating-point data before addition. The floating-point numbers are accumulated by repeating the above operation.
摘要翻译：为了获得足够精确的浮点积累结果，即使计算量很大，根据本发明的浮点累加器如下构成：当两个浮点数据存储在任何移位寄存器中时，两个数据分别通过连接到缓冲器移位寄存器的一个BUS0和BUS1输出。两个输出数据通过BUS0和BUS1输入加法器，并在添加浮点数后作为相加结果数据输出。上述相加的结果数据通过BUSW和多路复用器返回到移位寄存器的每个输入，并且在相加之前通过移位寄存器保持浮点数据之一来写入与移位寄存器相对应的移位寄存器。通过重复上述操作来累积浮点数。

5. 发明授权

US4780807A Pipeline processor with overlapped fetch and execute cycles 失效
标题翻译：管道处理器重叠获取和执行周期
公开(公告)号：US4780807A
公开(公告)日：1988-10-25
申请号：US85244
申请日：1987-08-11
申请人： Shinjiro Toyoda
发明人： Shinjiro Toyoda
IPC分类号： G06F9/38 , G06F7/00 , G06F9/30 , G06F15/78 , G06F13/00 , G11C7/00
CPC分类号： G06F15/8076
摘要： This pipeline processor has an ALU, an accumulator register, a first data bus connected through a first switch circuit to output terminals of the accumulator register, and a second data bus connected to input terminals of the accumulator register through a second switch circuit. Data on the first data base is processed by the ALU, and supplied through a third switch circuit to the second data bus. First to third switch circuits respectively receive first to third control signals generated at a predetermined timing for controlling the data transfer by the signal generator of an execution control circuit. The execution control circuit is further provided with signal generator for generating a fourth control signal which renders the second switch circuit conductive during the precharge period of the first and second data buses. The third and fourth control signals are supplied through an OR gate to the second switch circuit.
摘要翻译：该流水线处理器具有ALU，累加器寄存器，通过第一开关电路连接到累加器寄存器的输出端的第一数据总线，以及通过第二开关电路连接到累加器寄存器的输入端的第二数据总线。第一数据库上的数据由ALU处理，并通过第三开关电路提供给第二数据总线。第一至第三开关电路分别接收在预定定时产生的控制由执行控制电路的信号发生器进行数据传送的第一至第三控制信号。执行控制电路还设置有信号发生器，用于产生使第二开关电路在第一和第二数据总线的预充电期间导通的第四控制信号。第三和第四控制信号通过或门提供给第二开关电路。

6. 发明授权

US5101283A Halftone image generating apparatus 失效
标题翻译：半色调图像生成装置
公开(公告)号：US5101283A
公开(公告)日：1992-03-31
申请号：US430235
申请日：1989-10-30
申请人： Masao Seki , Kazuyasu Sasuga , Yukiharu Inoue , Shinjiro Toyoda
发明人： Masao Seki , Kazuyasu Sasuga , Yukiharu Inoue , Shinjiro Toyoda
IPC分类号： B41J2/52 , B41J2/525 , G06T5/00 , H04N1/00 , H04N1/32 , H04N1/405 , H04N1/52
CPC分类号： H04N1/4058 , H04N1/00411 , H04N1/00416 , H04N1/00424 , H04N1/00453 , H04N1/32561 , H04N1/32609
摘要： A halftone image generating apparatus for use in a halftone image generating system for generating threshold value data corresponding to positions in a main scanning direction and a subsidiary scanning direction, comprising a threshold value data generating circuit for generating the threshold value data in a matrix pattern having a variable number of lines and rows, and for converting input picture image data having chromatic gradations into binary value data by comparing the input picture image data to the threshold value data, and a circuit for forming a scanning mesh dot image corresponding to the input picture image data.
摘要翻译：一种半色调图像生成装置，用于半色调图像生成系统，用于产生与主扫描方向和副扫描方向上的位置相对应的阈值数据，包括阈值数据产生电路，用于以矩阵模式生成阈值数据，可变数量的行和行，并且通过将输入图像图像数据与阈值数据进行比较，将具有色度等级的输入图像图像数据转换为二进制值数据，以及用于形成与输入图像相对应的扫描网格点图像的电路图像数据。

7. 发明授权

US5596511A Computing method and apparatus for a many-body problem 失效
标题翻译：多体问题的计算方法和装置
公开(公告)号：US5596511A
公开(公告)日：1997-01-21
申请号：US186029
申请日：1994-01-25
申请人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F19/701
摘要： A proximal particle list including numbers of particles located within a predetermined distance from a particular particle is generated in calculating a Coulomb force acting on a particular particle or a related potential. A van der Waals force acting on the particular particle or a related potential is thereafter calculated based on only the particles included in the proximal particle list.
摘要翻译：在计算作用于特定颗粒或相关电位的库仑力时，产生包括位于特定颗粒的预定距离内的颗粒数的近端粒子列表。此后，仅基于近端粒子列表中包含的粒子计算作用于特定粒子或相关电位的范德华力。

8. 发明授权

US4504926A Mode setting control system 失效
标题翻译：模式设定控制系统
公开(公告)号：US4504926A
公开(公告)日：1985-03-12
申请号：US365894
申请日：1982-04-06
申请人： Shinjiro Toyoda
发明人： Shinjiro Toyoda
IPC分类号： G06F13/10 , G06F1/22 , G06F15/78 , G06F3/00
CPC分类号： G06F1/22
摘要： A mode setting control system comprising a one-chip microprocessor and a mode setting circuit provided outside the microprocessor. The mode setting circuit comprises mode designating switches, diodes and a flip-flop. Data representing the mode designated by the switches is written into the one-chip microprocessor through I/O pins. After the one-chip microprocessor has been brought out of the reset state, an ADR signal is supplied from the one-chip microprocessor through an ADR pin thereof, whichever operation mode the microprocessor is set to. The ADR signal is supplied to the mode setting circuit, thus electrically disconnecting the same from the one-chip microprocessor. Consequently, data other than the mode data can be written into the I/O pins.
摘要翻译：一种模式设置控制系统，包括设置在微处理器外部的单片微处理器和模式设置电路。模式设置电路包括模式指定开关，二极管和触发器。表示由开关指定的模式的数据通过I / O引脚写入单片微处理器。在单片微处理器已经退出复位状态之后，ADR信号由单片微处理器通过其ADR引脚提供，无论哪个操作模式被设置为微处理器。 ADR信号被提供给模式设置电路，从而将其与单片微处理器电连接。因此，模式数据以外的数据可以写入I / O引脚。

9. 发明授权

US4485456A Data processor with R/W memory write inhibit signal 失效
标题翻译：具有R / W存储器的数据处理器写禁止信号
公开(公告)号：US4485456A
公开(公告)日：1984-11-27
申请号：US369359
申请日：1982-04-19
申请人： Shinjiro Toyoda
发明人： Shinjiro Toyoda
IPC分类号： G06F12/16 , G06F1/26 , G11C7/24 , H02J9/00 , G06F13/00
CPC分类号： G11C7/24
摘要： A main power source voltage is compared with a reference voltage, when the main power voltage drops lower than the reference voltage, an operation/halt signal is formed, a read/write memory write inhibit signal is formed in response to the operation/halt signal, and the read/write memory is inhibited in operation. This write inhibit signal is formed by setting a D-type latch at the timing of the transition of the NIF signal to active mode.
摘要翻译：将主电源电压与参考电压进行比较，当主电源电压降低到参考电压以下时，形成操作/停止信号，响应于操作/停止信号形成读/写存储器写禁止信号，并且在操作中禁止读/写存储器。该写禁止信号是通过在NIF信号转换到活动模式的定时设置D型锁存器来形成的。

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