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    • 1. 发明申请
    • Nucleic acid detecting sensor, nucleic acid detecting chip, and nucleic acid detecting circuit
    • 核酸检测传感器,核酸检测芯片和核酸检测电路
    • US20060147983A1
    • 2006-07-06
    • US11366472
    • 2006-03-03
    • Shin-ichi O'uchi
    • Shin-ichi O'uchi
    • C12Q1/68C12M1/34
    • G01N27/4145
    • Nucleic acid detecting sensor includes field-effect transistor, detector which detects target nucleic acid molecules having sequences from sample based on degree of a variation in threshold voltage of field-effect transistor, and at least one nucleic acid probe molecule which is hybridized with corresponding one of target nucleic acid molecules, and is immobilized on gate of field-effect transistor, wherein gate width of field-effect transistor is of order of length obtained by expression given below (ε0εrkBT/e2n)1/2 where ε0 is dielectric constant of vacuum, εr is relative dielectric constant of channel region, kB is Boltzmann constant, T is absolute temperature of the channel region, e is elementary charge, and n is equilibrium carrier density in the channel region in field-effect transistor where channel is formed.
    • 核酸检测传感器包括场效应晶体管,检测器,其基于场效应晶体管的阈值电压的变化程度检测具有来自样品的序列的靶核酸分子,以及与相应的一个核酸分子杂交的至少一个核酸探针分子 的靶核酸分子,并且固定在场效应晶体管的栅极上,其中场效应晶体管的栅极宽度是通过下面给出的表达式获得的长度的数量级(ε-εεε 其中ε是真空的介电常数,ε是相对介电常数,ε= 通道区域,kB是玻尔兹曼常数,T是通道区域的绝对温度,e是基本电荷,n是形成通道的场效应晶体管的沟道区域中的平衡载流子密度。
    • 2. 发明授权
    • Semiconductor calculation device
    • 半导体计算装置
    • US06963079B2
    • 2005-11-08
    • US10488925
    • 2002-09-10
    • Minoru FujishimaShin-ichi O'UchiKoichiro Hoh
    • Minoru FujishimaShin-ichi O'UchiKoichiro Hoh
    • G06F7/00G06F15/16G06F15/173G06F15/80G06N99/00H01L29/06
    • G06N99/002B82Y10/00G06F15/8007Y10S977/933
    • A parallel processor including two processor element groups each configured to simultaneously execute arithmetic operations for states of all logical values expressable by N bits (N is a natural number) and retain results of the arithmetic operation to execute an arithmetic operation equivalent to N qubits; and an exchange unit for data exchange between the two processor element groups. The two processor element groups are each configured to execute an arithmetic operation equivalent to N qubits are connected to each other via the exchange unit to constitute a processor element group configured to execute an arithmetic operation equivalent to (N+1) qubits with 1 qubit extension, and consequently, it becomes possible to execute a large-scale arithmetic operation at high speed without any increase in the time and effort required for designing an integrated circuit for executing the large-scale arithmetic operation.
    • 一种并行处理器,包括两个处理器元件组,每个处理器元件组被配置为对由N个比特(N是自然数)表示的所有逻辑值的状态同时执行算术运算,并保留算术运算的结果,以执行等同于N个量子位的算术运算; 以及用于两个处理器单元组之间的数据交换的交换单元。 两个处理器单元组分别被配置为执行等价于N个量子位的算术运算,经由交换单元彼此连接,以构成处理器单元组,其被配置为执行等同于具有1个量子比特扩展的(N + 1)量子位的算术运算 因此,可以高速执行大规模的算术运算,而不用增加设计用于执行大规模运算的集成电路所需的时间和精力。