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    • 3. 发明授权
    • Display apparatus
    • 显示装置
    • US08836209B2
    • 2014-09-16
    • US13475148
    • 2012-05-18
    • Seung Hwan BaekMyeong-Ju ShinYeongbae Lee
    • Seung Hwan BaekMyeong-Ju ShinYeongbae Lee
    • G09F13/20
    • G09F13/04G09F13/20
    • A display apparatus includes a backlight unit which generates first light including first blue light, first green light and first red light and a display panel which receives the first light to display an image, where the backlight unit includes: a light emitting diode which generates an ultraviolet ray; a fluorescent substance layer disposed on the light emitting diode, where the fluorescent substance layer includes: a blue fluorescent substance layer which receives the ultraviolet ray and emits blue light; a green fluorescent substance layer which receives the ultraviolet ray and emits green light; and a red fluorescent substance layer which receives the ultraviolet ray and emits red light; and a first band-pass filter which receives the blue light, the green light and the red light and outputs the first blue light, the first green light and the first red light.
    • 显示装置包括产生包括第一蓝光,第一绿光和第一红光的第一光的背光单元和接收第一光以显示图像的显示面板,其中背光单元包括:发光二极管,其产生 紫外线 布置在所述发光二极管上的荧光物质层,其中所述荧光物质层包括:接收所述紫外线并发出蓝色光的蓝色荧光物质层; 接收紫外线并发出绿光的绿色荧光物质层; 和接收紫外线并发出红光的红色荧光物质层; 以及第一带通滤波器,其接收蓝色光,绿色光和红色光,并输出第一蓝色光,第一绿色光和第一红色光。
    • 8. 发明授权
    • Delay-locked loop circuit and method of generating multiplied clock therefrom
    • 延迟锁定环路电路和从其产生相乘时钟的方法
    • US07602223B2
    • 2009-10-13
    • US11877187
    • 2007-10-23
    • Seung-Hwan BaekSeung-Won Lee
    • Seung-Hwan BaekSeung-Won Lee
    • H03L7/06
    • H03L7/0812H03L7/0891H03L7/113H03L7/16
    • A delay-locked loop circuit includes: a phase detector generating a detection signal from a phase difference between an external clock signal and a feedback clock signal; a charge pump controlling a level of a voltage signal in response to the detection signal; and a voltage-controlled delay line generating a plurality of delay clock signals by delaying the external clock signal in response to the voltage signal and generating a multiplied clock signal using the delay clock signals in different numbers in accordance with a frequency domain of the external clock signal. The multiplied clock signal is generated by multiplying the external clock signal an integer number of times and the feedback clock signal is delayed from the plurality of delay clock signals by a cycle period of the external clock signal.
    • 延迟锁定环路电路包括:相位检测器,从外部时钟信号和反馈时钟信号之间的相位差产生检测信号; 电荷泵,响应于检测信号控制电压信号的电平; 以及电压控制延迟线,通过响应于电压信号延迟外部时钟信号并且根据外部时钟的频域使用不同数量的延迟时钟信号产生倍增时钟信号来产生多个延迟时钟信号 信号。 乘法时钟信号通过将外部时钟信号乘以整数倍而产生,反馈时钟信号从多个延迟时钟信号延迟外部时钟信号的周期。
    • 9. 发明申请
    • Output circuit of a source driver, and method of outputting data in a source driver
    • 源驱动器的输出电路,以及在源驱动器中输出数据的方法
    • US20070290983A1
    • 2007-12-20
    • US11808322
    • 2007-06-08
    • Hyung-Tae KimSeung-Hwan Baek
    • Hyung-Tae KimSeung-Hwan Baek
    • G09G3/36
    • G09G3/3685G09G2330/06
    • An output circuit of a source driver may include a first buffer adapted to receive a first voltage and to output a first sub-voltage, a second buffer adapted to receive a second voltage and to output a second sub-voltage, the second sub-voltage being complementary with the first sub-voltage, and a sharing signal generator adapted to generate a sharing signal, the sharing signal being activated when the first sub-voltage level and the second sub-voltage level begin to change, and being inactivated when the first sub-voltage level and the second sub-voltage level reach a reference level, wherein the sharing signal controls a state of an electrical path between an output terminal of the first buffer and an output terminal of the second buffer.
    • 源极驱动器的输出电路可以包括适于接收第一电压并输出第一子电压的第一缓冲器,适于接收第二电压并输出第二子电压的第二缓冲器,第二子电压 与第一子电压互补,以及适于产生共享信号的共享信号发生器,当第一子电压电平和第二子电压电平开始改变时,共享信号被激活,并且当第一子电压 子电压电平和第二子电压电平达到参考电平,其中共享信号控制第一缓冲器的输出端子和第二缓冲器的输出端子之间的电气路径的状态。