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1. 发明授权

US08043922B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08043922B2
公开(公告)日：2011-10-25
申请号：US12696886
申请日：2010-01-29
申请人： Jun-bum Lee , Tae-hong Ha , Seong-hwee Cheong
发明人： Jun-bum Lee , Tae-hong Ha , Seong-hwee Cheong
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/823425 , H01L27/1052 , H01L27/11536 , H01L29/6653
摘要： A method of fabricating a semiconductor device, can be provided by forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region. An offset spacer can be formed including a first material on the gate structures. A first ion implantation can be done using the gate structures and the offset spacer as an ion implantation mask to form source/drain regions. A material layer can be formed including a second material on the semiconductor substrate and on the gate structures. A material layer can be formed of a third material, having an etch selectivity with respect to the second material, on the material layer of the second material. An etch-back can be performed the material layer comprising the third material in the cell region and in the peripheral region, to simultaneously expose the source/drains region in the peripheral region and not expose the source/drain regions in the cell region.
摘要翻译：可以通过在单元区域和外围电路区域中的半导体衬底上形成用于晶体管的栅极结构来提供制造半导体器件的方法。可以在栅极结构上形成包括第一材料的偏移间隔物。可以使用栅极结构和偏移间隔物作为离子注入掩模来进行第一离子注入以形成源极/漏极区域。可以在半导体衬底上和门结构上形成包括第二材料的材料层。材料层可以由第二材料的材料层上具有相对于第二材料的蚀刻选择性的第三材料形成。可以在单元区域和外围区域中执行包括第三材料的材料层的回蚀，以同时暴露外围区域中的源极/漏极区域，并且不暴露电池区域中的源极/漏极区域。

2. 发明申请

US20110171818A1 METHODS OF FORMING A GATE STRUCTURE 有权
标题翻译：形成门结构的方法
公开(公告)号：US20110171818A1
公开(公告)日：2011-07-14
申请号：US13053923
申请日：2011-03-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A method of forming a gate structure can be provided by forming a tunnel insulation layer on a substrate and forming a floating gate on the tunnel insulation layer. A dielectric layer pattern can be on the floating gate and a control gate can be formed on the dielectric layer pattern, which can be provided by forming a first conductive layer pattern on the dielectric layer pattern. A metal ohmic layer pattern can be formed on the first conductive layer pattern. A diffusion preventing layer pattern can be formed on the metal ohmic layer pattern. An amorphous layer pattern can be formed on the diffusion preventing layer pattern forming a second conductive layer pattern on the amorphous layer pattern. The floating gate can be further formed by forming an additional first conductive layer pattern on the tunnel insulation layer. An additional metal ohmic layer pattern can be formed on the additional first conductive layer pattern. An additional diffusion preventing layer can be formed pattern on the additional metal ohmic layer pattern. An additional amorphous layer pattern can be formed on the additional diffusion preventing layer pattern and an additional second conductive layer pattern can be formed on the additional amorphous layer pattern.
摘要翻译：可以通过在衬底上形成隧道绝缘层并在隧道绝缘层上形成浮栅来提供形成栅极结构的方法。电介质层图案可以在浮动栅极上，并且可以在介电层图案上形成控制栅极，其可以通过在电介质层图案上形成第一导电层图案来提供。可以在第一导电层图案上形成金属欧姆层图案。可以在金属欧姆层图案上形成扩散防止层图案。可以在形成非晶层图案上的第二导电层图案的扩散防止层图案上形成非晶层图案。可以通过在隧道绝缘层上形成附加的第一导电层图案来进一步形成浮栅。另外的金属欧姆层图案可以形成在附加的第一导电层图案上。附加的扩散防止层可以在附加金属欧姆层图案上形成图案。可以在附加的防扩散层图案上形成附加的非晶层图案，并且可以在附加的非晶层图案上形成附加的第二导电层图案。

3. 发明申请

US20090189229A1 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090189229A1
公开(公告)日：2009-07-30
申请号：US12315436
申请日：2008-12-03
申请人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
发明人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
IPC分类号： H01L21/283 , H01L23/532 , H01L29/78
CPC分类号： H01L21/28061 , H01L29/4933
摘要： Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.
摘要翻译：提供半导体器件及其制造方法，更具体地说，具有低电阻的W-Ni合金薄层的半导体器件及其制造方法。半导体器件包括W-Ni合金薄层。 W-Ni合金薄层中的Ni的重量可以在W-Ni合金薄层的总重量的约0.01〜约5.0重量％的范围内。

4. 发明申请

US20060246710A1 Methods of fabricating semiconductor devices including contact plugs having laterally extending portions and related devices 有权
标题翻译：制造半导体器件的方法，包括具有横向延伸部分的接触插塞和相关器件
公开(公告)号：US20060246710A1
公开(公告)日：2006-11-02
申请号：US11409685
申请日：2006-04-24
申请人： Seong-Hwee Cheong , Gil-Heyun Choi , Sang-Woo Lee , Jin-Ho Park
发明人： Seong-Hwee Cheong , Gil-Heyun Choi , Sang-Woo Lee , Jin-Ho Park
IPC分类号： H01L21/4763 , H01L21/76
CPC分类号： H01L27/1108 , H01L21/28562 , H01L21/76802 , H01L21/76843 , H01L21/76846 , H01L27/0688 , H01L27/11
摘要： In a method of forming an integrated circuit device, an opening is formed extending through a first and a second insulating layers and through a semiconductor layer therebetween to a surface of a substrate. The opening includes a recess in a sidewall thereof between the first and second insulating layers adjacent the semiconductor layer. A conductive plug is formed on the sidewall of the opening and on the surface of the substrate and laterally extending into the recess between the first and second insulating layers to contact the semiconductor layer. The semiconductor layer may be selectively etched at the sidewall without substantially etching the first and second insulating layers at the sidewall of the opening to form the recess between the first and second insulating layers. Related devices are also discussed.
摘要翻译：在形成集成电路器件的方法中，形成延伸穿过第一和第二绝缘层并且穿过其间的半导体层到基板表面的开口。开口包括在与半导体层相邻的第一和第二绝缘层之间的侧壁中的凹部。导电插塞形成在开口的侧壁和基板的表面上，并横向延伸到第一和第二绝缘层之间的凹部中以接触半导体层。可以在侧壁处选择性地蚀刻半导体层，而不必在开口的侧壁基本上蚀刻第一和第二绝缘层，以在第一和第二绝缘层之间形成凹部。还讨论了相关设备。

5. 发明申请

US20050196945A1 Methods of forming a double metal salicide layer and methods of fabricating semiconductor devices incorporating the same 有权
标题翻译：形成双金属硅化物层的方法及其制造的半导体器件的制造方法
公开(公告)号：US20050196945A1
公开(公告)日：2005-09-08
申请号：US11044884
申请日：2005-01-27
申请人： Jong-ho Yun , Gil-heyun Choi , Seong-hwee Cheong , Sug-woo Jung , Hyun-su Kim , Woong-hee Sohn
发明人： Jong-ho Yun , Gil-heyun Choi , Seong-hwee Cheong , Sug-woo Jung , Hyun-su Kim , Woong-hee Sohn
IPC分类号： H01L21/24 , H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconductor device is annealed to react the double metal layer with the silicon surface. At least a portion of the double layer that has not reacted with the silicon surface is stripped. The semiconductor device is annealed after stripping at least the portion of the double metal layer.
摘要翻译：通过在具有暴露的硅表面的半导体器件上依次沉积物理气相沉积（PVD）金属层和化学气相沉积（CVD）金属层以形成双金属层来形成金属硅化物层。将半导体器件退火以使双金属层与硅表面反应。剥离未与硅表面反应的双层的至少一部分。半导体器件在剥离至少双重金属层的部分之后进行退火。

6. 发明申请

US20090315091A1 GATE STRUCTURE, AND SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE 有权
标题翻译：门结构和具有门结构的半导体器件
公开(公告)号：US20090315091A1
公开(公告)日：2009-12-24
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L29/49 , H01L27/10
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模

7. 发明申请

US20080003711A1 METHOD OF FABRICATING NONVOLATILE MEMORY DEVICE 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080003711A1
公开(公告)日：2008-01-03
申请号：US11686205
申请日：2007-03-14
申请人： Seong-Hwee CHEONG , Sang-Woo LEE , Jin-Ho PARK , Seung-Gil YANG , Brad H. LEE
发明人： Seong-Hwee CHEONG , Sang-Woo LEE , Jin-Ho PARK , Seung-Gil YANG , Brad H. LEE
IPC分类号： H01L21/00
CPC分类号： H01L21/28282 , B82Y10/00 , H01L29/4234
摘要： In one embodiment, a nonvolatile memory device can be fabricated by forming first metallic dots on a charge storage film using first source gas, forming substitution dots on the charge storage film on which the first metallic dots are formed and forming second metallic dots using a second source gas.
摘要翻译：在一个实施例中，可以通过使用第一源气体在电荷存储膜上形成第一金属点来形成非易失性存储器件，在形成有第一金属点的电荷存储膜上形成取代点，并使用第二金属点形成第二金属点源气。

8. 发明授权

US08466052B2 Method of fabricating semiconductor device having buried wiring 有权
标题翻译：制造具有埋地布线的半导体器件的方法
公开(公告)号：US08466052B2
公开(公告)日：2013-06-18
申请号：US12704358
申请日：2010-02-11
申请人： Jong-min Baek , Hee-sook Park , Seong-hwee Cheong , Gil-heyun Choi , Byung-hak Lee , Tae-ho Cha , Jae-hwa Park , Su-kyoung Kim
发明人： Jong-min Baek , Hee-sook Park , Seong-hwee Cheong , Gil-heyun Choi , Byung-hak Lee , Tae-ho Cha , Jae-hwa Park , Su-kyoung Kim
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/321 , H01L21/3213
CPC分类号： H01L27/10891
摘要： A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.
摘要翻译：制造半导体器件的方法可以包括在半导体衬底中形成沟槽，在沟槽的底表面和侧表面上形成第一导电层，并且在第一导电层上选择性地形成第二导电层以埋在沟。可以通过使用化学镀方法或使用金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）方法在第一导电层上选择性地形成第二导电层。

9. 发明授权

US07989892B2 Gate structure, and semiconductor device having a gate structure 有权
标题翻译：栅极结构和具有栅极结构的半导体器件
公开(公告)号：US07989892B2
公开(公告)日：2011-08-02
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/44
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer.
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模。

10. 发明授权

US07781849B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07781849B2
公开(公告)日：2010-08-24
申请号：US12315436
申请日：2008-12-03
申请人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
发明人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
IPC分类号： H01L29/78 , H01L23/48 , H01L23/52 , H01L29/40 , H01L29/49
CPC分类号： H01L21/28061 , H01L29/4933
摘要： Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.
摘要翻译：提供半导体器件及其制造方法，更具体地说，具有低电阻的W-Ni合金薄层的半导体器件及其制造方法。半导体器件包括W-Ni合金薄层。 W-Ni合金薄层中的Ni的重量可以在W-Ni合金薄层的总重量的约0.01〜约5.0重量％的范围内。

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