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1. 发明授权

US08557661B2 Methods of manufacturing a semiconductor device and a semiconductor memory device thereby 有权
标题翻译：因此制造半导体器件和半导体存储器件的方法
公开(公告)号：US08557661B2
公开(公告)日：2013-10-15
申请号：US13314627
申请日：2011-12-08
申请人： Han-Geun Yu , Gyung-Jin Min , Seong-Soo Lee , Suk-Ho Joo , Yoo-Chul Kong , Dae-Hyun Jang
发明人： Han-Geun Yu , Gyung-Jin Min , Seong-Soo Lee , Suk-Ho Joo , Yoo-Chul Kong , Dae-Hyun Jang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/11565 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L27/11575 , H01L27/11582
摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.
摘要翻译：一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到形成一个楼梯形状 d侧边缘部分。

2. 发明申请

US20120187471A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR MEMORY DEVICE THEREBY 有权
标题翻译：制造半导体器件的方法和半导体存储器件
公开(公告)号：US20120187471A1
公开(公告)日：2012-07-26
申请号：US13314627
申请日：2011-12-08
申请人： Han-Geun YU , Gyung-Jin MIN , Seong-Soo LEE , Suk-Ho JOO , Yoo-Chul KONG , Dae-Hyun JANG
发明人： Han-Geun YU , Gyung-Jin MIN , Seong-Soo LEE , Suk-Ho JOO , Yoo-Chul KONG , Dae-Hyun JANG
IPC分类号： H01L29/78 , H01L21/336 , H01L21/308
CPC分类号： H01L27/11565 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L27/11575 , H01L27/11582
摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.
摘要翻译：一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到形成一个楼梯形状 d侧边缘部分。

3. 发明授权

US07933320B2 Communication system using length shift keying modulation method 有权
标题翻译：通信系统采用长移键控调制方式
公开(公告)号：US07933320B2
公开(公告)日：2011-04-26
申请号：US11499700
申请日：2006-08-07
申请人： Jae-hyon Kim , Young-hwan Kim , Seong-soo Lee
发明人： Jae-hyon Kim , Young-hwan Kim , Seong-soo Lee
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04L27/00
摘要： A communication system using a length shift keying (LSK) modulation method provides a transmitter having a carrier signal generator for generating carrier signals, and a modulator for modulating lengths of the carrier signals from the carrier signal generator according to combinations of data bits, and a receiver having an integrator for calculating an energy value by integrating the carrier signal that corresponds to a data bit combination, and a data judgment unit for judging the data bit combination by comparing the energy value with a predetermined threshold value. Power is maintained without changing the bandwidth of a communication signal when the communication signal is modulated.
摘要翻译：使用长移键控（LSK）调制方法的通信系统提供具有用于产生载波信号的载波信号发生器的发射机，以及用于根据数据比特的组合来调制来自载波信号发生器的载波信号长度的调制器，具有用于通过对与数据位组合相对应的载波信号进行积分来计算能量值的积分器的接收机，以及用于通过将能量值与预定阈值进行比较来判断数据比特组合的数据判断单元。当通信信号被调制时，维持功率而不改变通信信号的带宽。

4. 发明授权

US07755214B2 Diode circuit having passive element property, impedance modulator including the diode circuit, and DC source including the diode circuit 有权
标题翻译：具有无源元件特性的二极管电路，包括二极管电路的阻抗调制器和包括二极管电路的直流电源
公开(公告)号：US07755214B2
公开(公告)日：2010-07-13
申请号：US11440042
申请日：2006-05-25
申请人： Seung-woo Kim , Seong-soo Lee , Jae-sup Lee
发明人： Seung-woo Kim , Seong-soo Lee , Jae-sup Lee
IPC分类号： H02J3/02
CPC分类号： H03F3/19 , H03F1/56 , Y10T307/25
摘要： A diode circuit having a passive element property, and an impedance modulator and a direct current (DC) source that use the diode circuit are provided. The diode circuit includes a first diode that generates a predetermined DC and alternating currents (AC) when a radio frequency (RF) signal is applied; and a DC path that is connected in parallel to the first diode, forms a predetermined loop and circulates the DC current within the loop. The DC path includes an inductor or an LC parallel resonator. The DC path includes a second diode that is disposed in the opposite direction to the first diode and connected to the first diode in parallel. The present invention can relieve difficulty in designing an RF circuit.
摘要翻译：提供具有无源元件特性的二极管电路以及使用二极管电路的阻抗调制器和直流（DC）源。二极管电路包括当应用射频（RF）信号时产生预定的DC和交流电流（AC）的第一二极管; 并且与第一二极管并联连接的DC路径形成预定的环路并使该直流电流循环。 DC路径包括电感器或LC并联谐振器。 DC路径包括与第一二极管相反的方向设置并并联连接到第一二极管的第二二极管。本发明可以减轻设计RF电路的难度。

5. 发明授权

US07449974B2 On-chip balun and transceiver using the same and method for fabricating on-chip balun 有权
标题翻译：片上平衡 - 不平衡变压器和收发器采用相同的方法制造片上平衡 - 不平衡转换器
公开(公告)号：US07449974B2
公开(公告)日：2008-11-11
申请号：US11330104
申请日：2006-01-12
申请人： Jae-sup Lee , Dong-hyun Lee , Seong-soo Lee
发明人： Jae-sup Lee , Dong-hyun Lee , Seong-soo Lee
IPC分类号： H03H5/00
CPC分类号： H01F17/0013 , H01F2017/008
摘要： Provided are an on-chip balun, a transceiver using the on-chip balun, and a method for fabricating the on-chip balun. The on-chip balun includes: a first metal winding including a port grounded and a port to which an unbalanced signal is input; a second winding outputting an induced current generated by the first metal winding as two signals having about equal intensity and a phase difference of about 180°; and a ground shield positioned between the first and second metal windings and having a symmetric structure so as to generate a symmetric parasitic capacitance between the ground shield and the second metal winding. The ground shield can be inserted between the first and second metal windings to remove an asymmetrical parasitic capacitance so as to reduce a phase imbalance and a gain imbalance of an output value of the second metal winding. As a result, a highly balanced on-chip balun can be fabricated.
摘要翻译：提供了片上平衡 - 不平衡转换器，使用片上平衡 - 不平衡转换器的收发器以及制造片上平衡 - 不平衡转换器的方法。片上平衡 - 不平衡变压器包括：第一金属绕组，其包括接地的端口和输入不平衡信号的端口; 输出由第一金属绕组产生的感应电流的第二绕组作为具有大约相同强度的两个信号和约180°的相位差; 以及位于第一和第二金属绕组之间并具有对称结构以便在接地屏蔽和第二金属绕组之间产生对称寄生电容的接地屏蔽。接地屏蔽可以插入在第一和第二金属绕组之间以去除不对称的寄生电容，以便减少相位不平衡和第二金属绕组的输出值的增益不平衡。因此，可以制造高度平衡的片上平衡 - 不平衡变压器。

6. 发明授权

US07414490B2 Dual-band voltage-controlled oscillator using bias switching and output-buffer multiplexing 有权
标题翻译：双频压控振荡器采用偏置开关和输出缓冲复用
公开(公告)号：US07414490B2
公开(公告)日：2008-08-19
申请号：US11288212
申请日：2005-11-29
申请人： Sang-yoon Jeon , Heung-bae Lee , Seong-soo Lee , Jinup Lim , Joongho Choi
发明人： Sang-yoon Jeon , Heung-bae Lee , Seong-soo Lee , Jinup Lim , Joongho Choi
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1209 , H03B5/1215 , H03B5/124
摘要： Disclosed is a dual-band voltage-controlled oscillator using bias switching and output-buffer multiplexing. The dual-band voltage-controlled oscillator includes a power supply unit for supplying a source voltage; plural voltage-controlled oscillation units for outputting different oscillation frequencies according to controls of a certain tuning voltage; plural bias units for generating driving voltages for driving the voltage-controlled oscillation units and supplying the driving voltages to the voltage-controlled oscillation units; and plural buffers for selectively outputting oscillation frequencies of the plural voltage-controlled oscillation units. The present invention implements the dual-band voltage-controlled oscillator through bias switching and output-buffer multiplexing, which brings an advantage of elimination of interference between output frequencies to enhance phase noise characteristics.
摘要翻译：公开了一种使用偏置开关和输出缓冲器复用的双频带压控振荡器。双频带压控振荡器包括用于提供源电压的电源单元; 多个电压控制振荡单元，用于根据某个调谐电压的控制输出不同的振荡频率; 多个偏压单元，用于产生用于驱动压控振荡单元的驱动电压并将驱动电压提供给压控振荡单元; 以及用于选择性地输出多个压控振荡单元的振荡频率的多个缓冲器。本发明通过偏置开关和输出缓冲多路复用来实现双频压控振荡器，其具有消除输出频率之间的干扰以增强相位噪声特性的优点。

7. 发明授权

US07348676B2 Semiconductor device having a metal wiring structure 有权
标题翻译：具有金属布线结构的半导体器件
公开(公告)号：US07348676B2
公开(公告)日：2008-03-25
申请号：US11149600
申请日：2005-06-09
申请人： Seong-Soo Lee
发明人： Seong-Soo Lee
IPC分类号： H01L23/48
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76838 , H01L21/76843 , H01L21/76847 , H01L21/76883 , H01L23/485 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a height substantially smaller than a depth of the contact hole. A metal wiring structure is formed on the recessed plug and on the insulation layer. A lower portion of the metal wiring structure, formed within the contact hole, prevents damage to the recessed plug during an etching process for forming the metal wiring structure. Therefore, the recessed plug may be formed without damage thereof even if an alignment error occurs between an etching mask and the recessed plug during metal wiring structure formation.
摘要翻译：在基板上形成绝缘层之后，通过绝缘层形成接触孔。形成一个凹形插头以部分地填充接触孔。凹形插塞的高度显着小于接触孔的深度。金属布线结构形成在凹形插塞和绝缘层上。形成在接触孔内的金属布线结构的下部防止了在用于形成金属布线结构的蚀刻工艺期间对凹形插塞的损坏。因此，即使在金属布线结构形成期间在蚀刻掩模和凹入插塞之间发生定向误差，也可以形成凹形插塞而不损坏凹形插塞。

8. 发明申请

US20080055139A1 DIGITAL MODULATION CIRCUIT 有权
标题翻译：数字调制电路
公开(公告)号：US20080055139A1
公开(公告)日：2008-03-06
申请号：US11847761
申请日：2007-08-30
申请人： Man Suk Seo , Hyung Cheol Park , Seong Soo Lee , Sang Yub Lee , Chang Soo Yang , Wan Cheol Yang
发明人： Man Suk Seo , Hyung Cheol Park , Seong Soo Lee , Sang Yub Lee , Chang Soo Yang , Wan Cheol Yang
IPC分类号： H03M1/66
CPC分类号： H03C3/02 , H03C1/02 , H03K7/04 , H03K2005/00247 , H04B1/71635
摘要： Provided is a digital modulation circuit constructed with only a digital circuit. The digital modulation circuit includes: a clock generator which generates a reference clock pulse having a predetermined period; an up/down counter which generates a count value having predetermined bits by up-counting or down-counting the reference clock pulse and outputs a bit in the count value as a transmission signal; a controller which determines a counting start/end time point of the up/down counter and determine which one of the up-counting operation and the down-counting operation of the up/down counter is to be performed, according to a value of digital transmission data that is to be transmitted; and a band-pass filter which converts a waveform of the transmission signal output from the up/down counter into a sine waveform.
摘要翻译：提供了仅由数字电路构成的数字调制电路。数字调制电路包括：时钟发生器，其产生具有预定周期的参考时钟脉冲; 向上/向下计数器，其通过对参考时钟脉冲进行向上计数或递减计数来产生具有预定位的计数值，并将计数值中的位作为发送信号输出; 确定上/下计数器的计数开始/结束时间点的控制器，并根据数字的数值确定要执行向上/向下计数器的向上计数操作和向下计数操作中的哪一个要发送的发送数据; 以及将从上/下计数器输出的发送信号的波形转换为正弦波形的带通滤波器。

9. 发明申请

US20070268106A1 Device for improving amplitude imbalance of on-chip transformer balun 有权
标题翻译：用于提高片上变压器平衡不平衡变压器幅度不平衡的器件
公开(公告)号：US20070268106A1
公开(公告)日：2007-11-22
申请号：US11540711
申请日：2006-10-02
申请人： Dong Hyun Lee , Sang Yoon Jeon , Seong Soo Lee , Heung Bae Lee , Hai Young Lee , Sung Ho Joo
发明人： Dong Hyun Lee , Sang Yoon Jeon , Seong Soo Lee , Heung Bae Lee , Hai Young Lee , Sung Ho Joo
IPC分类号： H01F5/00
CPC分类号： H03H7/42 , H01F27/2804 , H01F27/34
摘要： An on-chip transformer balun includes a primary winding as an input terminal of the on-chip transformer balun, and a secondary winding as an output terminal of the on-chip transformer balun, wherein one of the primary winding and secondary winding is formed of a plurality of metal layers in which a spiral trace portion excluding an underpass is disposed on mutually different layers to have an asymmetrical structure.
摘要翻译：片上变压器平衡 - 不平衡变压器包括作为片上变压器平衡不平衡转换器的输入端子的初级绕组和作为片上变压器平衡 - 不平衡转换器的输出端子的次级绕组，其中初级绕组和次级绕组中的一个由多个金属层，其中除了地下通道之外的螺旋迹线部分设置在相互不同的层上以具有不对称结构。

10. 发明授权

US07274335B2 Antenna for slide-type wireless terminal device 有权
标题翻译：天线用于滑盖型无线终端设备
公开(公告)号：US07274335B2
公开(公告)日：2007-09-25
申请号：US11442529
申请日：2006-05-30
申请人： Yong-jin Kim , Do-hoon Kwon , Seong-soo Lee , Young-eil Kim
发明人： Yong-jin Kim , Do-hoon Kwon , Seong-soo Lee , Young-eil Kim
IPC分类号： H01Q1/24
CPC分类号： H01Q1/243 , H01Q9/42
摘要： An antenna for a slide-type wireless terminal device includes a radiator formed in a first body, a ground surface formed on a second body, a power feeder connected to the ground surface in the second body, a first connection part connected to the radiator in the first body and operative to come in contact with the power feeder when the first body is slidably moved, and a short-circuit wire operative to come in contact with the radiator and the ground surface when the first body is slidably moved.
摘要翻译：一种用于滑盖式无线终端装置的天线，包括形成在第一主体中的散热器，形成在第二主体上的接地面，连接到第二主体中的接地面的电力馈送器，连接到散热器的第一连接部所述第一主体在所述第一主体可滑动地移动时与所述供电装置接触，并且当所述第一主体可滑动地移动时可操作地与所述散热器和所述接地表面接触的短路线。

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