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1. 发明授权

US07723199B2 Method for cleaning post-etch noble metal residues 有权
标题翻译：蚀刻后贵金属残留物的方法
公开(公告)号：US07723199B2
公开(公告)日：2010-05-25
申请号：US11669759
申请日：2007-01-31
申请人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
发明人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
IPC分类号： H01L21/02
CPC分类号： H01L21/02071 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/022 , H01L21/02263 , H01L21/31683 , H01L28/55 , H01L28/65
摘要： A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.
摘要翻译：提出了制造半导体器件的方法。一方面，该方法包括在半导体衬底上形成导电和铁电材料层。图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。转化还包括氧化金属氢氧化物以形成非导电金属氧化物。

2. 发明申请

US20090275148A1 MITIGATION OF EDGE DEGRADATION IN FERROELECTRIC MEMORY DEVICES THROUGH PLASMA ETCH CLEAN 有权
公开(公告)号：US20090275148A1
公开(公告)日：2009-11-05
申请号：US12502571
申请日：2009-07-14
申请人： Kezhakkedath R. UDAYAKUMAR , Lindsey H. HALL , Francis G. CELII
发明人： Kezhakkedath R. UDAYAKUMAR , Lindsey H. HALL , Francis G. CELII
IPC分类号： H01L21/00
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.

3. 发明申请

US20070281422A1 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权
标题翻译：通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化
公开(公告)号：US20070281422A1
公开(公告)日：2007-12-06
申请号：US11442810
申请日：2006-05-30
申请人： Kezhakkedath R. Udayakumar , Lindsey H. Hall , Francis G. Celii , Scott R. Summerfelt
发明人： Kezhakkedath R. Udayakumar , Lindsey H. Hall , Francis G. Celii , Scott R. Summerfelt
IPC分类号： H01L21/336
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译：制造铁电存储器件，同时减轻边缘退化。在一个或多个半导体层上形成底部电极。在底部电极上形成铁电层。顶部电极形成在铁电层上。上电极，铁电层和底电极被图案化或蚀刻。进行干洗以减轻边缘退化。然后进行湿蚀刻/清洁。

4. 发明申请

US20090275147A1 MITIGATION OF EDGE DEGRADATION IN FERROELECTRIC MEMORY DEVICES THROUGH PLASMA ETCH CLEAN 有权
标题翻译：通过等离子体清洁来减少电磁记忆装置中的边缘降解
公开(公告)号：US20090275147A1
公开(公告)日：2009-11-05
申请号：US12502523
申请日：2009-07-14
申请人： Kezhakkedath R. UDAYAKUMAR , Lindsey H. HALL , Francis G. CELII , Scott R. SUMMERFELT
发明人： Kezhakkedath R. UDAYAKUMAR , Lindsey H. HALL , Francis G. CELII , Scott R. SUMMERFELT
IPC分类号： H01L21/00
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译：制造铁电存储器件，同时减轻边缘退化。在一个或多个半导体层上形成底部电极。在底部电极上形成铁电层。顶部电极形成在铁电层上。上电极，铁电层和底电极被图案化或蚀刻。进行干洗以减轻边缘退化。然后进行湿蚀刻/清洁。

5. 发明授权

US07517779B2 Recessed drain extensions in transistor device 有权
标题翻译：晶体管器件中的凹槽漏极延伸
公开(公告)号：US07517779B2
公开(公告)日：2009-04-14
申请号：US11772508
申请日：2007-07-02
申请人： Lindsey H. Hall
发明人： Lindsey H. Hall
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/165 , H01L21/823412 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.
摘要翻译：一种形成集成电路晶体管（50）的方法。该方法提供第一半导体区域（52）并且形成（110）相对于第一半导体区域处于固定位置的栅极结构（54x）。栅极结构具有第一侧壁和第二侧壁（59x）。该方法还形成与第一侧壁和第二侧壁相邻的至少第一层（58x，60x）。该方法还在第一半导体区域中形成（120）至少一个凹部（62x）并且从栅极结构横向向外延伸。该方法中的附加步骤首先是氧化（130）所述至少一个凹部，使得在其中形成氧化材料，其次，剥离（140）所述氧化材料的至少一部分，以及第三，形成（160）第二半导体区域（66x）。

6. 发明授权

US07422967B2 Method for manufacturing a semiconductor device containing metal silicide regions 有权
标题翻译：制造含有金属硅化物区域的半导体器件的方法
公开(公告)号：US07422967B2
公开(公告)日：2008-09-09
申请号：US11127669
申请日：2005-05-12
申请人： Juanita DeLoach , Lindsey H. Hall , Lance S. Robertson , Jiong-Ping Lu , Donald S. Miles
发明人： Juanita DeLoach , Lindsey H. Hall , Lance S. Robertson , Jiong-Ping Lu , Donald S. Miles
IPC分类号： H01L21/3205
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).
摘要翻译：本发明提供一种制造半导体器件的方法。在本发明的一个实施例中，但不限于，用于制造半导体器件的方法包括在衬底（110）上形成栅极结构（120）并且在靠近栅极的衬底（110）中形成源/漏区（190）结构（120）。该方法还包括在源极/漏极区（190）中使用含氟等离子体，使用小于约75瓦特的功率电平形成含氟区域（220），在基底（110）上形成金属层（310），以及含氟区域（220），并且使金属层（310）与含氟区域（220）反应以在源极/漏极区域（190）中形成金属硅化物区域（410）。

7. 发明授权

US06372648B1 Integrated circuit planarization method 有权
标题翻译：集成电路平面化方法
公开(公告)号：US06372648B1
公开(公告)日：2002-04-16
申请号：US09442181
申请日：1999-11-16
申请人： Lindsey H. Hall , Jennifer A. Sees
发明人： Lindsey H. Hall , Jennifer A. Sees
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , C09G1/02 , C09K3/1463
摘要： Chemical mechanical polishing slurry with functionalized silica abrasive particles, the functionalization permits high pH slurry without rapid degradation of silica particles and also permits the modification of surface properties of abrasive particles to modify slurry behavior. One example of modified behavior would be to enhance selectivity by controlling particle interaction with different surfaces on the wafer.
摘要翻译：具有功能化二氧化硅磨料颗粒的化学机械抛光浆料，功能化允许高pH浆料，而不会快速降解二氧化硅颗粒，并且还允许改变磨料颗粒的表面性质以改变浆料性能。改进行为的一个例子是通过控制与晶片上的不同表面的颗粒相互作用来提高选择性。

8. 发明授权

US6145372A Apparatus and method for detecting impurities in wet chemicals 失效
标题翻译：用于检测湿化学品中杂质的装置和方法
公开(公告)号：US6145372A
公开(公告)日：2000-11-14
申请号：US069908
申请日：1998-04-30
申请人： Lindsey H. Hall , Jennifer Sees , Oliver Chyan
发明人： Lindsey H. Hall , Jennifer Sees , Oliver Chyan
IPC分类号： G01N27/416 , G01N33/00 , G01N27/403
CPC分类号： G01N27/4166 , G01N2033/0095
摘要： A apparatus and method for monitoring impurities in wet chemicals in semiconductor wafer processing comprising a silicon sensor (12) that is electrically connected to a potentiometer (22), a reference electrode (14) electrically connected to the potentiometer (22), wherein a comparison in the potential between the silicon sensor (12) and the reference electrode (14) to a predetermined baseline is used to measure wet chemical impurities, is disclosed.
摘要翻译：一种用于监测半导体晶片处理中的湿化学品中的杂质的装置和方法，包括电连接到电位器（22）的硅传感器（12），与电位计（22）电连接的参考电极（14），其中比较在硅传感器（12）和参考电极（14）之间的电位达到预定的基线用于测量湿化学杂质。

9. 发明申请

US20140073131A1 METHOD TO IMPROVE SEMICONDUCTOR SURFACES AND POLISHING 有权
标题翻译：改善半导体表面和抛光的方法
公开(公告)号：US20140073131A1
公开(公告)日：2014-03-13
申请号：US13609292
申请日：2012-09-11
申请人： Lindsey H. Hall , Michael Hatzistergos , Ahmet S. Ozcan , Filippos Papadatos , Yiyi Wang
发明人： Lindsey H. Hall , Michael Hatzistergos , Ahmet S. Ozcan , Filippos Papadatos , Yiyi Wang
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/32115 , H01L21/32135 , H01L21/76831 , H01L21/7684 , H01L21/76871 , H01L21/76892
摘要： A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.
摘要翻译：公开了一种形成半导体器件的方法。所述方法包括提供其上设置有至少一个绝缘层的衬底，所述至少一个绝缘层包括沟槽; 在所述至少一个绝缘层上形成至少一个衬垫层; 在所述至少一个衬垫层上形成成核层; 在成核层的表面上形成第一金属膜; 蚀刻第一金属膜; 以及在所述第一金属膜的蚀刻表面上沉积第二金属膜，所述第二金属膜基本上形成在所述沟槽上方的覆盖层。

10. 发明授权

US07572698B2 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权
标题翻译：通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化
公开(公告)号：US07572698B2
公开(公告)日：2009-08-11
申请号：US11442810
申请日：2006-05-30
申请人： Kezhakkedath R. Udayakumar , Lindsey H. Hall , Francis G. Celii , Scott R. Summerfelt
发明人： Kezhakkedath R. Udayakumar , Lindsey H. Hall , Francis G. Celii , Scott R. Summerfelt
IPC分类号： H01L21/336
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译：制造铁电存储器件，同时减轻边缘退化。在一个或多个半导体层上形成底部电极。在底部电极上形成铁电层。顶部电极形成在铁电层上。上电极，铁电层和底电极被图案化或蚀刻。进行干洗以减轻边缘退化。然后进行湿蚀刻/清洁。

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