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1. 发明授权

US07757194B1 Method and system for generating implementation files from a high level specification 有权
标题翻译：从高级规范生成实现文件的方法和系统
公开(公告)号：US07757194B1
公开(公告)日：2010-07-13
申请号：US11903013
申请日：2007-09-19
申请人： Mark B. Roberts , Scott K. Roberts
发明人： Mark B. Roberts , Scott K. Roberts
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method and system for generating implementation files from a high level specification are described. In one example, a method for creating a package file for an integrated circuit is described. First, a grid is formed having a plurality of blocks. A height and a width are then determined for each block. At least one bump is placed on a block and a corresponding package pin is assigned to the at least one bump. Finally, the package file is output.
摘要翻译：描述用于从高级别规范生成实现文件的方法和系统。在一个示例中，描述了用于创建集成电路的封装文件的方法。首先，形成具有多个块的网格。然后为每个块确定高度和宽度。至少一个凸起被放置在块上，并且相应的封装销被分配给所述至少一个凸块。最后，输出包文件。

2. 发明授权

US07765508B1 Method and system for generating multiple implementation views of an IC design 有权
标题翻译：用于生成IC设计的多个实现视图的方法和系统
公开(公告)号：US07765508B1
公开(公告)日：2010-07-27
申请号：US11971003
申请日：2008-01-08
申请人： Mark B. Roberts , Scott K. Roberts
发明人： Mark B. Roberts , Scott K. Roberts
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on an integrated circuit (IC) in which all elements in a row have the same height and all elements in a column have the same width. This array, which may be displayed in a textual or spreadsheet format, forms the high-level placement specification. A software program of this embodiment converts this high-level placement specification into layout and schematic files that can be used by a commercial CAD tool to produce a file for fabrication.
摘要翻译：公开了一种用于从高级布局规范生成布局和示意性实施数据的方法和系统。此外，还可以生成打包数据和软件模型。在一个实施例中，行和列的阵列形成在集成电路（IC）中，其中一行中的所有元件具有相同的高度，并且列中的所有元件具有相同的宽度。可以以文本或电子表格格式显示的该数组形成高级放置规范。该实施例的软件程序将该高级放置规范转换成可由商业CAD工具使用以生产用于制造的文件的布局和原理图文件。

3. 发明授权

US07334209B1 Method and system for generating multiple implementation views of an IC design 失效
标题翻译：用于生成IC设计的多个实现视图的方法和系统
公开(公告)号：US07334209B1
公开(公告)日：2008-02-19
申请号：US10966554
申请日：2004-10-15
申请人： Mark B. Roberts , Scott K. Roberts
发明人： Mark B. Roberts , Scott K. Roberts
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on an integrated circuit (IC) in which all elements in a row have the same height and all elements in a column have the same width. This array, which may be displayed in a textual or spreadsheet format, forms the high-level placement specification. A software program of this embodiment converts this high-level placement specification into layout and schematic files that can be used by a commercial CAD tool to produce a file for fabrication.
摘要翻译：公开了一种用于从高级布局规范生成布局和示意性实施数据的方法和系统。此外，还可以生成打包数据和软件模型。在一个实施例中，行和列的阵列形成在集成电路（IC）中，其中一行中的所有元件具有相同的高度，并且列中的所有元件具有相同的宽度。可以以文本或电子表格格式显示的该数组形成高级放置规范。该实施例的软件程序将该高级放置规范转换成可由商业CAD工具使用以生产用于制造的文件的布局和原理图文件。

4. 发明授权

US6078528A Delay control circuit using dynamic latches 有权
标题翻译：延迟控制电路采用动态锁存器
公开(公告)号：US6078528A
公开(公告)日：2000-06-20
申请号：US339463
申请日：1999-06-23
申请人： Robert Anders Johnson , Richard A. Carberry , Scott K. Roberts
发明人： Robert Anders Johnson , Richard A. Carberry , Scott K. Roberts
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22
摘要： Dynamic latches for writing to a synchronous RAM are controlled by a clock signal and a delay circuit so that the dynamic latches will not stay in a latched state for more than a selected time interval regardless of the clock signal. One delay circuit limits the length of a write enable signal. Another delay circuit responds to the write enable signal and after a delay returns the address and data latches to their transparent states.
摘要翻译：用于写入同步RAM的动态锁存器由时钟信号和延迟电路控制，使得无论时钟信号如何，动态锁存器将不会停留在超过选定时间间隔的锁存状态。一个延迟电路限制写使能信号的长度。另一个延迟电路响应写入使能信号，并且延迟后将地址和数据锁存器返回到其透明状态。

5. 发明授权

US07308656B1 Method and apparatus for generating a boundary scan description and model 有权
标题翻译：用于生成边界扫描描述和模型的方法和装置
公开(公告)号：US07308656B1
公开(公告)日：2007-12-11
申请号：US11243713
申请日：2005-10-04
申请人： Scott K. Roberts , Mark B. Roberts
发明人： Scott K. Roberts , Mark B. Roberts
IPC分类号： G06F17/50 , G06F11/22 , G01R31/28 , G01R31/3187
CPC分类号： G01R31/318536 , G01R31/318544 , G01R31/318591
摘要： An aspect of the invention relates to a method, apparatus, and computer-readable medium for processing schematic data for an integrated circuit having a boundary scan architecture. A path through cells of the schematic data to generate a hierarchy of cells associated with a boundary scan chain. Each ignore cell in the hierarchy is pruned. Each short cell in the hierarchy is replaced with a direct connection. A shadow net is added to each net of the hierarchy. Each of the cells in the hierarchy is flattened in a bottom-up fashion.
摘要翻译：本发明的一个方面涉及一种用于处理具有边界扫描结构的集成电路的原理图数据的方法，装置和计算机可读介质。通过原理图数据的单元格的路径，以生成与边界扫描链相关联的单元格层次结构。每个忽略层次结构中的单元格被修剪。层次结构中的每个短单元格都被替换为直接连接。将一个影子网添加到层次结构的每个网络。层次结构中的每个单元格以自下而上的方式展开。

6. 发明授权

US07284227B1 Method and system for generating implementation files from a high level specification 失效
标题翻译：从高级规范生成实现文件的方法和系统
公开(公告)号：US07284227B1
公开(公告)日：2007-10-16
申请号：US10966993
申请日：2004-10-15
申请人： Mark B. Roberts , Scott K. Roberts
发明人： Mark B. Roberts , Scott K. Roberts
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on an integrated circuit (IC) in which all elements in a row have the same height and all elements in a column have the same width. This array, which may be displayed in a textual or spreadsheet format, forms the high-level placement specification. A software program of this embodiment converts this high-level placement specification into layout and schematic files that can be used by a commercial CAD tool to produce a file for fabrication.
摘要翻译：公开了一种用于从高级布局规范生成布局和示意性实施数据的方法和系统。此外，还可以生成打包数据和软件模型。在一个实施例中，行和列的阵列形成在集成电路（IC）中，其中一行中的所有元件具有相同的高度，并且列中的所有元件具有相同的宽度。可以以文本或电子表格格式显示的该数组形成高级放置规范。该实施例的软件程序将该高级放置规范转换成可由商业CAD工具使用以生产用于制造的文件的布局和原理图文件。

7. 发明授权

US5933369A RAM with synchronous write port using dynamic latches 失效
标题翻译： RAM具有使用动态锁存器的同步写入端口
公开(公告)号：US5933369A
公开(公告)日：1999-08-03
申请号：US808447
申请日：1997-02-28
申请人： Robert Anders Johnson , Richard A. Carberry , Scott K. Roberts
发明人： Robert Anders Johnson , Richard A. Carberry , Scott K. Roberts
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22
摘要： Dynamic latches for writing to a synchronous RAM are controlled by a clock signal and a delay circuit so that the dynamic latches will not stay in a latched state for more than a selected time interval regardless of the clock signal. One delay circuit limits the length of a write enable signal. Another delay circuit responds to the write enable signal and after a delay returns the address and data latches to their transparent states.
摘要翻译：用于写入同步RAM的动态锁存器由时钟信号和延迟电路控制，使得无论时钟信号如何，动态锁存器将不会停留在超过选定时间间隔的锁存状态。一个延迟电路限制写使能信号的长度。另一个延迟电路响应写入使能信号，并且延迟后将地址和数据锁存器返回到其透明状态。

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