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1. 发明授权

US09780096B2 Vertical memory devices and methods of manufacturing the same 有权
公开(公告)号：US09780096B2
公开(公告)日：2017-10-03
申请号：US14965532
申请日：2015-12-10
申请人： Sang-yong Park , Kee-jeong Rho , Hyeong Park , Tae-wan Lim
发明人： Sang-yong Park , Kee-jeong Rho , Hyeong Park , Tae-wan Lim
IPC分类号： H01L23/528 , H01L29/423 , H01L29/792 , H01L27/108 , H01L23/31 , H01L27/11568 , H01L27/11573 , H01L27/11582 , H01L29/78 , H01L27/1157 , H01L27/11575
CPC分类号： H01L27/10897 , H01L23/3171 , H01L23/3185 , H01L23/528 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/42352 , H01L29/4236 , H01L29/7827 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

2. 发明授权

US09213347B2 Low-dropout regulator, power management system, and method of controlling low-dropout voltage 有权
标题翻译：低压差稳压器，电源管理系统以及低压差电压控制方法
公开(公告)号：US09213347B2
公开(公告)日：2015-12-15
申请号：US14556110
申请日：2014-11-29
申请人： Je-Kook Kim , Sang-Yong Park , Chan-Woo Park , Young-Hoon Lee , Byeong-Ha Park
发明人： Je-Kook Kim , Sang-Yong Park , Chan-Woo Park , Young-Hoon Lee , Byeong-Ha Park
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： A low-dropout regulator comprises an analog-to-digital converter that converts a feedback analog voltage signal into a digital signal, a phase synthesizing unit that generates a first control signal having a pulse width corresponding to error information in the digital signal by performing phase synthesis according to clock skew control, a charge pump circuit that selects a charge loop or a discharge loop based on polarity information in the digital signal, and generates an output control voltage according to current that flows during a period corresponding to the pulse width of the first control signal in the selected loop, and an output circuit that generates an output voltage based on an input voltage and the output control voltage, and generates the feedback analog voltage signal based on the output voltage.
摘要翻译：低压差稳压器包括将反馈模拟电压信号转换为数字信号的模数转换器，相位合成单元，通过执行相位产生具有对应于数字信号中的误差信息的脉冲宽度的第一控制信号根据时钟偏移控制进行合成的电荷泵电路，根据数字信号中的极性信息选择充电回路或放电回路的电荷泵电路，并根据在与脉冲宽度对应的周期期间流动的电流产生输出控制电压所选择的回路中的第一控制信号，以及基于输入电压和输出控制电压产生输出电压的输出电路，并且基于输出电压生成反馈模拟电压信号。

3. 发明授权

US09117654B2 Methods of forming fine patterns in integrated circuit devices 有权
标题翻译：在集成电路器件中形成精细图案的方法
公开(公告)号：US09117654B2
公开(公告)日：2015-08-25
申请号：US13470773
申请日：2012-05-14
申请人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
发明人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
IPC分类号： H01L21/467 , H01L27/02 , H01L21/033 , H01L21/308 , H01L21/3213 , H01L21/762 , H01L23/544 , H01L27/115 , H01L27/105
CPC分类号： H01L27/0207 , H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L21/32139 , H01L21/76229 , H01L23/544 , H01L27/1052 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.
摘要翻译：制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。间隔件形成在第一和第二掩模结构的相对侧壁上。第一掩模结构被选择性地从第一区域中的间隔物之间移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案在第二区域中。

4. 发明申请

US20150177758A1 LOW-DROPOUT REGULATOR, POWER MANAGEMENT SYSTEM, AND METHOD OF CONTROLLING LOW-DROPOUT VOLTAGE 有权
标题翻译：低压差稳压器，电源管理系统和控制低压差电压的方法
公开(公告)号：US20150177758A1
公开(公告)日：2015-06-25
申请号：US14556110
申请日：2014-11-29
申请人： JE-KOOK KIM , SANG-YONG PARK , CHAN-WOO PARK , YOUNG-HOON LEE , BYEONG-HA PARK
发明人： JE-KOOK KIM , SANG-YONG PARK , CHAN-WOO PARK , YOUNG-HOON LEE , BYEONG-HA PARK
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： A low-dropout regulator comprises an analog-to-digital converter that converts a feedback analog voltage signal into a digital signal, a phase synthesizing unit that generates a first control signal having a pulse width corresponding to error information in the digital signal by performing phase synthesis according to clock skew control, a charge pump circuit that selects a charge loop or a discharge loop based on polarity information in the digital signal, and generates an output control voltage according to current that flows during a period corresponding to the pulse width of the first control signal in the selected loop, and an output circuit that generates an output voltage based on an input voltage and the output control voltage, and generates the feedback analog voltage signal based on the output voltage.
摘要翻译：低压差稳压器包括将反馈模拟电压信号转换为数字信号的模数转换器，相位合成单元，通过执行相位产生具有对应于数字信号中的误差信息的脉冲宽度的第一控制信号根据时钟偏移控制进行合成的电荷泵电路，根据数字信号中的极性信息选择充电回路或放电回路的电荷泵电路，并根据在与脉冲宽度对应的周期期间流动的电流产生输出控制电压所选择的回路中的第一控制信号，以及基于输入电压和输出控制电压产生输出电压的输出电路，并且基于输出电压生成反馈模拟电压信号。

5. 发明申请

US20150060993A1 NONVOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE NONVOLATILE MEMORY DEVICE, AND MEMORY MODULE AND SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件，非易失性存储器件的制造方法以及包含非易失性存储器件的存储器模块和系统
公开(公告)号：US20150060993A1
公开(公告)日：2015-03-05
申请号：US14529940
申请日：2014-10-31
申请人： Jae-goo Lee , Young-woo Park , Byung-kwan You , Dong-sik Lee , Sang-yong Park
发明人： Jae-goo Lee , Young-woo Park , Byung-kwan You , Dong-sik Lee , Sang-yong Park
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L29/66477 , H01L29/7926
摘要： A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.
摘要翻译：非易失性存储器件包括衬底，从衬底突出的沟道层，围绕沟道层的栅极导电层，设置在沟道层和栅极导电层之间的栅极绝缘层以及与沟道间隔开的第一绝缘层并设置在栅极导电层的顶部和底部。栅极绝缘层在栅极导电层和第一绝缘层之间延伸。

6. 发明授权

US08906805B2 Methods of fabricating semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08906805B2
公开(公告)日：2014-12-09
申请号：US13418585
申请日：2012-03-13
申请人： Sang-yong Park , Woon-kyung Lee , Jin-taek Park
发明人： Sang-yong Park , Woon-kyung Lee , Jin-taek Park
IPC分类号： H01L21/768 , H01L29/788 , H01L29/792 , H01L27/115
CPC分类号： H01L21/76802 , H01L21/311 , H01L21/76838 , H01L21/76877 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n−1 first recesses penetrating 20 through 2n−1 deposited sacrificial layers and forming a buried insulating layer group including 2n−1 buried insulating layers filling the 2n−1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n−1 buried insulating layers may be formed.
摘要翻译：一种制造半导体器件的方法包括形成层叠结构，其中分别沉积有牺牲层的2n（n为2以上的整数）和设置在2n个沉积的牺牲层上的2n个沉积的绝缘层交替地沉积在第三垂直于第一方向和第二方向的方向在具有在彼此垂直的第一和第二方向上延伸的上表面的基板上。方法包括形成包括通过2n-1个沉积的牺牲层穿透20的2n-1个第一凹部的凹陷组，并且分别形成包括2n-1个第一凹部的2n-1个掩埋绝缘层的掩埋绝缘层组。可以形成包括穿过2n个沉积绝缘层的最上层的绝缘层和2n-1个绝缘层的2n个接触插塞的接触插塞组。

7. 发明授权

US08877626B2 Nonvolatile memory device, method of manufacturing the nonvolatile memory device, and memory module and system including the nonvolatile memory device 有权
标题翻译：非易失性存储器件，非易失性存储器件的制造方法以及包括非易失性存储器件的存储器模块和系统
公开(公告)号：US08877626B2
公开(公告)日：2014-11-04
申请号：US13896819
申请日：2013-05-17
申请人： Jae-goo Lee , Young-woo Park , Byung-kwan You , Dong-sik Lee , Sang-yong Park
发明人： Jae-goo Lee , Young-woo Park , Byung-kwan You , Dong-sik Lee , Sang-yong Park
IPC分类号： H01L21/3205 , H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L29/66477 , H01L29/7926
摘要： A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.
摘要翻译：非易失性存储器件包括衬底，从衬底突出的沟道层，围绕沟道层的栅极导电层，设置在沟道层和栅极导电层之间的栅极绝缘层以及与沟道间隔开的第一绝缘层并设置在栅极导电层的顶部和底部。栅极绝缘层在栅极导电层和第一绝缘层之间延伸。

8. 发明申请

US20140211897A1 METHODS AND APPARATUS FOR GENERATING CLOCK SIGNALS BY NORMALIZING DUTY CODE TO PERIOD CODE 有权
标题翻译：通过将代码定义为定期代码来生成时钟信号的方法和装置
公开(公告)号：US20140211897A1
公开(公告)日：2014-07-31
申请号：US14154731
申请日：2014-01-14
申请人： Je Kook Kim , Sang Yong Park , Chan Woo Park , Young Hoon Lee , Byeong Ha Park
发明人： Je Kook Kim , Sang Yong Park , Chan Woo Park , Young Hoon Lee , Byeong Ha Park
IPC分类号： H04L7/04
CPC分类号： G06F1/04 , G06F1/08 , H03K5/1565 , H04L7/04
摘要： A clock signal generating method includes receiving a duty code that represents a duty of a clock signal, and a period code that represents a period of a clock signal, and normalizing the duty code to the period code to output a normalized duty code. The clock signal generating method further includes controlling a rising timing of a clock signal in response to the period code, and controlling a falling timing of the clock signal in response to the normalized duty code to generate a timing-controlled clock signal.
摘要翻译：时钟信号产生方法包括：接收表示时钟信号的占空比的占空比代码，以及表示时钟信号的周期的周期代码，并且将占空比规范化为周期代码以输出归一化的占空比代码。时钟信号产生方法还包括响应于周期代码来控制时钟信号的上升定时，以及响应于归一化的占空比代码来控制时钟信号的下降定时以产生定时控制的时钟信号。

9. 发明申请

US20140191405A1 METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的图案的方法
公开(公告)号：US20140191405A1
公开(公告)日：2014-07-10
申请号：US14208456
申请日：2014-03-13
申请人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
发明人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
IPC分类号： H01L23/528
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/76229 , H01L21/76816 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/11519 , H01L27/11526 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.
摘要翻译：提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。去除多个牺牲掩模图案。通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

10. 发明授权

US08318603B2 Method of forming patterns for semiconductor device 有权
标题翻译：形成半导体器件图案的方法
公开(公告)号：US08318603B2
公开(公告)日：2012-11-27
申请号：US12653588
申请日：2009-12-16
申请人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
发明人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
IPC分类号： H01L21/311
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/76229 , H01L21/76816 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/11519 , H01L27/11526 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.
摘要翻译：提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。去除多个牺牲掩模图案。通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

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