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1. 发明授权

US07860468B2 Programmable variable gain amplifier and RF receiver including the same 有权
标题翻译：可编程可变增益放大器和射频接收器包括相同
公开(公告)号：US07860468B2
公开(公告)日：2010-12-28
申请号：US11933504
申请日：2007-11-01
申请人： Il-Ku Nam , Byeong-Ha Park , Jong-Dae Bae , Jung-Wook Heo , Ho-Jung Ju , Hyun-Won Mun , Jeong-Hyun Choi
发明人： Il-Ku Nam , Byeong-Ha Park , Jong-Dae Bae , Jung-Wook Heo , Ho-Jung Ju , Hyun-Won Mun , Jeong-Hyun Choi
IPC分类号： H04B1/04 , H04B1/06
CPC分类号： H03F3/19 , H03F1/32 , H03F2200/294 , H03G1/0029 , H03G1/0088
摘要： A programmable variable gain amplifier includes at least three amplifiers. A first amplifier is configured to amplify an input signal. A second amplifier, which includes a programmable output load stage, is configured to receive an output signal from the first amplifier and to output a first differential output signal. The output load stage includes multiple first switches and multiple first diode-connected transistors that are open-circuited or short-circuited by the first switches. A third amplifier, which includes a programmable current mirror input stage, is configured to receive the first differential output signal from the second amplifier through the current mirror input stage and to output a second differential output signal. The current mirror input stage includes multiple second switches and multiple second transistors that are open-circuited or short-circuited by the plurality of second switches. The second transistors respectively form current mirrors with the first diode-connected transistors corresponding to the second transistors.
摘要翻译：可编程可变增益放大器包括至少三个放大器。第一放大器被配置为放大输入信号。包括可编程输出负载级的第二放大器被配置为从第一放大器接收输出信号并输出第一差分输出信号。输出负载级包括由第一开关断开或短路的多个第一开关和多个第一二极管连接的晶体管。包括可编程电流镜输入级的第三放大器被配置为通过电流镜输入级从第二放大器接收第一差分输出信号并输出第二差分输出信号。电流反射镜输入级包括多个第二开关和由多个第二开关断路或短路的多个第二晶体管。第二晶体管分别形成与第二晶体管对应的第一二极管连接的晶体管的电流镜。

2. 发明申请

US20100225361A1 FREQUENCY DIVIDER, FREQUENCY SYNTHESIZER AND APPLICATION CIRCUIT 有权
标题翻译：频率分频器，频率合成器和应用电路
公开(公告)号：US20100225361A1
公开(公告)日：2010-09-09
申请号：US12499978
申请日：2009-07-09
申请人： Woogeun RHEE , Xueyi YU , Yuanfeng SUN , Sang-Soo KO , Byeong-Ha PARK , Hyung-Ki AHN , Woo-Seung CHOO , Zhihua WANG
发明人： Woogeun RHEE , Xueyi YU , Yuanfeng SUN , Sang-Soo KO , Byeong-Ha PARK , Hyung-Ki AHN , Woo-Seung CHOO , Zhihua WANG
IPC分类号： H03B21/00 , H03B19/00 , H03K21/00
CPC分类号： H03K23/667 , H03K23/507
摘要： A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.
摘要翻译：分频器包括通常耦合到预分频器的预分频器和多模式分频器。预分频器响应于振荡频率信号产生相对于彼此具有相同相位差的中频信号。预分频器以第一频率工作。模数分频器分别以相应的比例分割中频信号以响应于控制信号提供多个分频信号。模数分频器以小于第一频率的第二频率工作。

3. 发明申请

US20080119154A1 PROGRAMMABLE VARIABLE GAIN AMPLIFIER AND RF RECEIVER INCLUDING THE SAME 有权
标题翻译：可编程可变增益放大器和RF接收器，包括它们
公开(公告)号：US20080119154A1
公开(公告)日：2008-05-22
申请号：US11933504
申请日：2007-11-01
申请人： Il-Ku NAM , Byeong-Ha PARK , Jong-Dae BAE , Jung-Wook HEO , Ho-Jung JU , Hyun-Won MUN , Jeong-Hyun CHOI
发明人： Il-Ku NAM , Byeong-Ha PARK , Jong-Dae BAE , Jung-Wook HEO , Ho-Jung JU , Hyun-Won MUN , Jeong-Hyun CHOI
IPC分类号： H03F3/45 , H04B1/16
CPC分类号： H03F3/19 , H03F1/32 , H03F2200/294 , H03G1/0029 , H03G1/0088
摘要： A programmable variable gain amplifier includes at least three amplifiers. A first amplifier is configured to amplify an input signal. A second amplifier, which includes a programmable output load stage, is configured to receive an output signal from the first amplifier and to output a first differential output signal. The output load stage includes multiple first switches and multiple first diode-connected transistors that are open-circuited or short-circuited by the first switches. A third amplifier, which includes a programmable current mirror input stage, is configured to receive the first differential output signal from the second amplifier through the current mirror input stage and to output a second differential output signal. The current mirror input stage includes multiple second switches and multiple second transistors that are open-circuited or short-circuited by the plurality of second switches. The second transistors respectively form current mirrors with the first diode-connected transistors corresponding to the second transistors.
摘要翻译：可编程可变增益放大器包括至少三个放大器。第一放大器被配置为放大输入信号。包括可编程输出负载级的第二放大器被配置为从第一放大器接收输出信号并输出第一差分输出信号。输出负载级包括由第一开关断开或短路的多个第一开关和多个第一二极管连接的晶体管。包括可编程电流镜输入级的第三放大器被配置为通过电流镜输入级从第二放大器接收第一差分输出信号并输出第二差分输出信号。电流反射镜输入级包括多个第二开关和由多个第二开关断路或短路的多个第二晶体管。第二晶体管分别形成与第二晶体管对应的第一二极管连接的晶体管的电流镜。

4. 发明授权

US06219397B1 Low phase noise CMOS fractional-N frequency synthesizer for wireless communications 失效
$Low phase noise CMOS fractional-N frequency synthesizer for wireless communications$
标题翻译：用于无线通信的低相位噪声CMOS分数N频率合成器
公开(公告)号：US06219397B1
公开(公告)日：2001-04-17
申请号：US09045192
申请日：1998-03-20
申请人： Byeong-Ha Park
发明人： Byeong-Ha Park
IPC分类号： H03D324
CPC分类号： H03L7/099 , H03K3/354 , H03K3/356139 , H03K3/35625 , H03K23/68 , H03L7/1978
摘要： A PLL-based CMOS fractional-N frequency synthesizer, which has an on-chip LC Voltage Controlled Oscillator. A higher-order discrete sigma-delta modulator is used in the fractional-N frequency synthesizer resulting in a strong attention at low frequencies for quantization noise. The synthesizer employs a noise shaping method to suppress fractional spurs using the high-order sigma-delta modulator.
摘要翻译：基于PLL的CMOS分数N频率合成器，其具有片上LC压控振荡器。在分数N频率合成器中使用高阶离散Σ-Δ调制器，导致在低频下对量化噪声的强烈关注。合成器采用噪声整形方法来抑制使用高阶Σ-Δ调制器的分数杂散。

5. 发明授权

US09213347B2 Low-dropout regulator, power management system, and method of controlling low-dropout voltage 有权
标题翻译：低压差稳压器，电源管理系统以及低压差电压控制方法
公开(公告)号：US09213347B2
公开(公告)日：2015-12-15
申请号：US14556110
申请日：2014-11-29
申请人： Je-Kook Kim , Sang-Yong Park , Chan-Woo Park , Young-Hoon Lee , Byeong-Ha Park
发明人： Je-Kook Kim , Sang-Yong Park , Chan-Woo Park , Young-Hoon Lee , Byeong-Ha Park
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： A low-dropout regulator comprises an analog-to-digital converter that converts a feedback analog voltage signal into a digital signal, a phase synthesizing unit that generates a first control signal having a pulse width corresponding to error information in the digital signal by performing phase synthesis according to clock skew control, a charge pump circuit that selects a charge loop or a discharge loop based on polarity information in the digital signal, and generates an output control voltage according to current that flows during a period corresponding to the pulse width of the first control signal in the selected loop, and an output circuit that generates an output voltage based on an input voltage and the output control voltage, and generates the feedback analog voltage signal based on the output voltage.
摘要翻译：低压差稳压器包括将反馈模拟电压信号转换为数字信号的模数转换器，相位合成单元，通过执行相位产生具有对应于数字信号中的误差信息的脉冲宽度的第一控制信号根据时钟偏移控制进行合成的电荷泵电路，根据数字信号中的极性信息选择充电回路或放电回路的电荷泵电路，并根据在与脉冲宽度对应的周期期间流动的电流产生输出控制电压所选择的回路中的第一控制信号，以及基于输入电压和输出控制电压产生输出电压的输出电路，并且基于输出电压生成反馈模拟电压信号。

6. 发明申请

US20150177758A1 LOW-DROPOUT REGULATOR, POWER MANAGEMENT SYSTEM, AND METHOD OF CONTROLLING LOW-DROPOUT VOLTAGE 有权
标题翻译：低压差稳压器，电源管理系统和控制低压差电压的方法
公开(公告)号：US20150177758A1
公开(公告)日：2015-06-25
申请号：US14556110
申请日：2014-11-29
申请人： JE-KOOK KIM , SANG-YONG PARK , CHAN-WOO PARK , YOUNG-HOON LEE , BYEONG-HA PARK
发明人： JE-KOOK KIM , SANG-YONG PARK , CHAN-WOO PARK , YOUNG-HOON LEE , BYEONG-HA PARK
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： A low-dropout regulator comprises an analog-to-digital converter that converts a feedback analog voltage signal into a digital signal, a phase synthesizing unit that generates a first control signal having a pulse width corresponding to error information in the digital signal by performing phase synthesis according to clock skew control, a charge pump circuit that selects a charge loop or a discharge loop based on polarity information in the digital signal, and generates an output control voltage according to current that flows during a period corresponding to the pulse width of the first control signal in the selected loop, and an output circuit that generates an output voltage based on an input voltage and the output control voltage, and generates the feedback analog voltage signal based on the output voltage.
摘要翻译：低压差稳压器包括将反馈模拟电压信号转换为数字信号的模数转换器，相位合成单元，通过执行相位产生具有对应于数字信号中的误差信息的脉冲宽度的第一控制信号根据时钟偏移控制进行合成的电荷泵电路，根据数字信号中的极性信息选择充电回路或放电回路的电荷泵电路，并根据在与脉冲宽度对应的周期期间流动的电流产生输出控制电压所选择的回路中的第一控制信号，以及基于输入电压和输出控制电压产生输出电压的输出电路，并且基于输出电压生成反馈模拟电压信号。

7. 发明申请

US20140211897A1 METHODS AND APPARATUS FOR GENERATING CLOCK SIGNALS BY NORMALIZING DUTY CODE TO PERIOD CODE 有权
标题翻译：通过将代码定义为定期代码来生成时钟信号的方法和装置
公开(公告)号：US20140211897A1
公开(公告)日：2014-07-31
申请号：US14154731
申请日：2014-01-14
申请人： Je Kook Kim , Sang Yong Park , Chan Woo Park , Young Hoon Lee , Byeong Ha Park
发明人： Je Kook Kim , Sang Yong Park , Chan Woo Park , Young Hoon Lee , Byeong Ha Park
IPC分类号： H04L7/04
CPC分类号： G06F1/04 , G06F1/08 , H03K5/1565 , H04L7/04
摘要： A clock signal generating method includes receiving a duty code that represents a duty of a clock signal, and a period code that represents a period of a clock signal, and normalizing the duty code to the period code to output a normalized duty code. The clock signal generating method further includes controlling a rising timing of a clock signal in response to the period code, and controlling a falling timing of the clock signal in response to the normalized duty code to generate a timing-controlled clock signal.
摘要翻译：时钟信号产生方法包括：接收表示时钟信号的占空比的占空比代码，以及表示时钟信号的周期的周期代码，并且将占空比规范化为周期代码以输出归一化的占空比代码。时钟信号产生方法还包括响应于周期代码来控制时钟信号的上升定时，以及响应于归一化的占空比代码来控制时钟信号的下降定时以产生定时控制的时钟信号。

8. 发明授权

US08446190B2 Frequency divider, frequency synthesizer and application circuit 有权
标题翻译：分频器，频率合成器和应用电路
公开(公告)号：US08446190B2
公开(公告)日：2013-05-21
申请号：US12499978
申请日：2009-07-09
申请人： Woogeun Rhee , Xueyi Yu , Yuanfeng Sun , Sang-Soo Ko , Byeong-Ha Park , Hyung-Ki Ahn , Woo-Seung Choo , Zhihua Wang
发明人： Woogeun Rhee , Xueyi Yu , Yuanfeng Sun , Sang-Soo Ko , Byeong-Ha Park , Hyung-Ki Ahn , Woo-Seung Choo , Zhihua Wang
IPC分类号： H03L7/06
CPC分类号： H03K23/667 , H03K23/507
摘要： A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.
摘要翻译：分频器包括通常耦合到预分频器的预分频器和多模式分频器。预分频器响应于振荡频率信号产生相对于彼此具有相同相位差的中频信号。预分频器以第一频率工作。模数分频器分别以相应的比例分割中频信号以响应于控制信号提供多个分频信号。模数分频器以小于第一频率的第二频率工作。

9. 发明授权

US07489200B2 Gain controllable low noise amplifier and wireless communication receiver having the same 有权
标题翻译：增益可控的低噪声放大器和具有相同功能的无线通信接收机
公开(公告)号：US07489200B2
公开(公告)日：2009-02-10
申请号：US11588651
申请日：2006-10-27
申请人： Jae-Hong Chang , Byeong-Ha Park , Sang-Yeob Lee , Seung-Chan Heo , Han-Gun Chung , Hyun-Won Mun , Min-Kyu Je , Seong-Han Ryu , Kwang-Seok Han
发明人： Jae-Hong Chang , Byeong-Ha Park , Sang-Yeob Lee , Seung-Chan Heo , Han-Gun Chung , Hyun-Won Mun , Min-Kyu Je , Seong-Han Ryu , Kwang-Seok Han
IPC分类号： H03F3/04
CPC分类号： H03F1/26 , H03F1/223 , H03F1/342 , H03F1/483 , H03F3/193 , H03F3/45183 , H03F2200/294 , H03F2200/42 , H03F2200/451 , H03F2200/54 , H03F2203/45511 , H03G3/3078
摘要： A gain controllable wide-band low noise amplifier includes a first transistor coupled to an input node and an output node and amplifying an input signal to generate an output signal, a second transistor allowing the output signal to feedback to the input node, and a control circuit complementarily controlling transconductance of the first and second transistors.
摘要翻译：增益可控宽带低噪声放大器包括耦合到输入节点的第一晶体管和输出节点，并放大输入信号以产生输出信号，允许输出信号反馈到输入节点的第二晶体管，以及控制电路互补地控制第一和第二晶体管的跨导。

10. 发明申请

US20070164826A1 Gain controllable low noise amplifier and wireless communication receiver having the same 有权
标题翻译：增益可控的低噪声放大器和具有相同功能的无线通信接收机
公开(公告)号：US20070164826A1
公开(公告)日：2007-07-19
申请号：US11588651
申请日：2006-10-27
申请人： Jae-Hong Chang , Byeong-Ha Park , Sang-Yeob Lee , Seung-Chan Heo , Han-Gun Chung , Hyun-Won Mun , Min-Kyu Je , Seong-Han Ryu , Kwang-Seok Han
发明人： Jae-Hong Chang , Byeong-Ha Park , Sang-Yeob Lee , Seung-Chan Heo , Han-Gun Chung , Hyun-Won Mun , Min-Kyu Je , Seong-Han Ryu , Kwang-Seok Han
IPC分类号： H03F1/22
CPC分类号： H03F1/26 , H03F1/223 , H03F1/342 , H03F1/483 , H03F3/193 , H03F3/45183 , H03F2200/294 , H03F2200/42 , H03F2200/451 , H03F2200/54 , H03F2203/45511 , H03G3/3078
摘要： A gain controllable wide-band low noise amplifier includes a first transistor coupled to an input node and an output node and amplifying an input signal to generate an output signal, a second transistor allowing the output signal to feedback to the input node, and a control circuit complementarily controlling transconductance of the first and second transistors.
摘要翻译：增益可控宽带低噪声放大器包括耦合到输入节点的第一晶体管和输出节点，并放大输入信号以产生输出信号，允许输出信号反馈到输入节点的第二晶体管，以及控制电路互补控制第一和第二晶体管的跨导。

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