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1. 发明授权

US09213347B2 Low-dropout regulator, power management system, and method of controlling low-dropout voltage 有权
标题翻译：低压差稳压器，电源管理系统以及低压差电压控制方法
公开(公告)号：US09213347B2
公开(公告)日：2015-12-15
申请号：US14556110
申请日：2014-11-29
申请人： Je-Kook Kim , Sang-Yong Park , Chan-Woo Park , Young-Hoon Lee , Byeong-Ha Park
发明人： Je-Kook Kim , Sang-Yong Park , Chan-Woo Park , Young-Hoon Lee , Byeong-Ha Park
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： A low-dropout regulator comprises an analog-to-digital converter that converts a feedback analog voltage signal into a digital signal, a phase synthesizing unit that generates a first control signal having a pulse width corresponding to error information in the digital signal by performing phase synthesis according to clock skew control, a charge pump circuit that selects a charge loop or a discharge loop based on polarity information in the digital signal, and generates an output control voltage according to current that flows during a period corresponding to the pulse width of the first control signal in the selected loop, and an output circuit that generates an output voltage based on an input voltage and the output control voltage, and generates the feedback analog voltage signal based on the output voltage.
摘要翻译：低压差稳压器包括将反馈模拟电压信号转换为数字信号的模数转换器，相位合成单元，通过执行相位产生具有对应于数字信号中的误差信息的脉冲宽度的第一控制信号根据时钟偏移控制进行合成的电荷泵电路，根据数字信号中的极性信息选择充电回路或放电回路的电荷泵电路，并根据在与脉冲宽度对应的周期期间流动的电流产生输出控制电压所选择的回路中的第一控制信号，以及基于输入电压和输出控制电压产生输出电压的输出电路，并且基于输出电压生成反馈模拟电压信号。

2. 发明授权

US09124172B2 Digital buck-boost conversion circuit and method of operating the same 有权
标题翻译：数字降压 - 升压转换电路及其操作方法
公开(公告)号：US09124172B2
公开(公告)日：2015-09-01
申请号：US13609376
申请日：2012-09-11
申请人： Je Kook Kim , Sang-Yong Park , Chan-Woo Park , Young Hoon Lee , Byung Chul Jeon , Min Shik Seok
发明人： Je Kook Kim , Sang-Yong Park , Chan-Woo Park , Young Hoon Lee , Byung Chul Jeon , Min Shik Seok
IPC分类号： H02M3/157 , H02M1/15 , H02M1/44 , H02M1/00 , H02M3/158
CPC分类号： H02M1/15 , H02M1/44 , H02M3/157 , H02M3/1582 , H02M2001/0012
摘要： A digital buck-boost conversion circuit includes an analog-to-digital converter configured to convert an output voltage signal into a digital signal, a pulse period control block configured to output a pulse period control signal based on degrees of scattering at different frequencies of the digital signal, a pulse generation block configured to output a pulse based on the pulse period control signal, and a buck-boost converter configured to convert the pulse into the output voltage signal.
摘要翻译：数字降压 - 升压转换电路包括被配置为将输出电压信号转换成数字信号的模数转换器，脉冲周期控制块，其被配置为基于在不同频率处的散射度输出脉冲周期控制信号数字信号，被配置为基于脉冲周期控制信号输出脉冲的脉冲发生块，以及配置成将脉冲转换成输出电压信号的降压 - 升压转换器。

3. 发明申请

US20140167290A1 METHODS OF FORMING FINE PATTERNS IN THE FABRICATION OF SEMICONDUCTOR DEVICES 有权
标题翻译：在半导体器件制造中形成精细图案的方法
公开(公告)号：US20140167290A1
公开(公告)日：2014-06-19
申请号：US14186617
申请日：2014-02-21
申请人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
发明人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
IPC分类号： H01L23/528
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76838 , H01L21/823456 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.
摘要翻译：在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是位于。模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。间隔层设置在第一区域和第二区域中的模具掩模图案上。执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征。

4. 发明授权

US08563378B2 Manufacturing semiconductor devices 有权
标题翻译：制造半导体器件
公开(公告)号：US08563378B2
公开(公告)日：2013-10-22
申请号：US13238104
申请日：2011-09-21
申请人： Jae-Joo Shim , Han-Soo Kim , Won-Seok Cho , Jae-Hoon Jang , Sang-Yong Park
发明人： Jae-Joo Shim , Han-Soo Kim , Won-Seok Cho , Jae-Hoon Jang , Sang-Yong Park
IPC分类号： H01L21/336
CPC分类号： H01L29/7831 , H01L27/11582 , H01L29/7926
摘要： A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.
摘要翻译：半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层之上，在最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。

5. 发明申请

US20060187212A1 User interface apparatus and method 审中-公开
标题翻译：用户界面设备和方法
公开(公告)号：US20060187212A1
公开(公告)日：2006-08-24
申请号：US11361720
申请日：2006-02-24
申请人： Sang-Yong Park , Seung-Gun Park , Sang-Hyuk Lee
发明人： Sang-Yong Park , Seung-Gun Park , Sang-Hyuk Lee
IPC分类号： G09G5/00
CPC分类号： G06F1/169 , G06F1/1616 , G06F1/1624 , G06F1/1662 , H04M1/72583 , H04M2250/22
摘要： A user interface apparatus comprises a plurality of key buttons, and a plurality of touchpad pieces, each located under an associated key button and situated such that a touch of an associated key button can be sensed. When a user touches predetermined key buttons among the plurality of key buttons such that the key buttons contact their associated touchpad pieces in a state where a menu screen is displayed, the predetermined key buttons serve as navigation key buttons for changing a menu screen between main menus or shifting a highlight between submenus. Upon detecting a touch-drag for a plurality of key buttons in a menu mode, menu items displayed on the menu screen are sorted or highlight-scrolled according to a predetermined condition for the touch-dragged key button group.
摘要翻译：用户接口装置包括多个按键按钮和多个触摸板部件，每个触摸板部件位于关联的键按钮下方并且被定位成使得可以感测到关联的键按钮的触摸。当用户触摸多个键按钮中的预定键按钮时，使得按键按钮在显示菜单屏幕的状态下与其相关联的触摸板块接触，预定键按钮用作用于改变主菜单之间的菜单屏幕的导航键按钮或在子菜单之间移动高亮。当在菜单模式下检测到多个按键按钮的触摸拖动时，根据触摸拖动键按钮组的预定条件对菜单屏幕上显示的菜单项进行排序或高亮显示滚动。

6. 发明申请

US20180076217A1 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20180076217A1
公开(公告)日：2018-03-15
申请号：US15813556
申请日：2017-11-15
申请人： Sang-Yong Park , Jintaek Park
发明人： Sang-Yong Park , Jintaek Park
IPC分类号： H01L27/11582 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L27/1157 , H01L27/11565 , H01L27/02 , H01L23/528 , H01L29/792 , H01L29/66 , H01L27/11578
摘要： A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

7. 发明授权

US08686563B2 Methods of forming fine patterns in the fabrication of semiconductor devices 有权
标题翻译：在半导体器件的制造中形成精细图案的方法
公开(公告)号：US08686563B2
公开(公告)日：2014-04-01
申请号：US12639542
申请日：2009-12-16
申请人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
发明人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76838 , H01L21/823456 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.
摘要翻译：在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是位于。模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。间隔层设置在第一区域和第二区域中的模具掩模图案上。执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征。

8. 发明申请

US20130072022A1 METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的图案的方法
公开(公告)号：US20130072022A1
公开(公告)日：2013-03-21
申请号：US13678930
申请日：2012-11-16
申请人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
发明人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
IPC分类号： H01L21/311
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/76229 , H01L21/76816 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/11519 , H01L27/11526 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.
摘要翻译：提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。去除多个牺牲掩模图案。通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

9. 发明申请

US20120070944A1 Methods of Manufacturing Three Dimensional Semiconductor Devices 审中-公开
标题翻译：制造三维半导体器件的方法
公开(公告)号：US20120070944A1
公开(公告)日：2012-03-22
申请号：US13231525
申请日：2011-09-13
申请人： Hyu-Jung Kim , Sang-Yong Park , JongHeun Lim , Kyunghyun Kim , ChangSup Mun
发明人： Hyu-Jung Kim , Sang-Yong Park , JongHeun Lim , Kyunghyun Kim , ChangSup Mun
IPC分类号： H01L21/822
CPC分类号： H01L21/822 , H01L27/0688 , H01L27/1052 , H01L27/11578 , H01L27/11582
摘要： Provided are methods of manufacturing a three dimensional semiconductor device. The method includes providing a substrate including a cell array region and a peripheral circuit region, forming a peripheral structure on the peripheral circuit region, forming a cell structure being thicker than the peripheral structure in the cell array region, forming an interlayer dielectric to cover the peripheral structure and the cell structure, forming a polishing stop layer on the interlayer dielectric, and planarizing the interlayer dielectric using the polishing stop layer as a planarization stop.
摘要翻译：提供制造三维半导体器件的方法。该方法包括提供包括单元阵列区域和外围电路区域的基板，在外围电路区域上形成周边结构，形成比单元阵列区域中的外围结构厚的单元结构，形成层间电介质以覆盖周边结构和电池结构，在层间电介质上形成抛光停止层，并且使用抛光停止层将层间电介质平坦化作为平坦化停止。

10. 发明申请

US20100096719A1 METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES 有权
标题翻译：在集成电路设备中形成精细图案的方法
公开(公告)号：US20100096719A1
公开(公告)日：2010-04-22
申请号：US12418023
申请日：2009-04-03
申请人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
发明人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
IPC分类号： H01L29/06 , H01L21/762 , H01L23/544
CPC分类号： H01L27/0207 , H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L21/32139 , H01L21/76229 , H01L23/544 , H01L27/1052 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature.
摘要翻译：制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。各向同性蚀刻第一和第二掩模结构的蚀刻掩模图案以从第一掩模结构去除蚀刻掩模图案，同时将蚀刻掩模图案的至少一部分保持在第二掩模结构上。间隔件形成在第一和第二掩模结构的相对侧壁上。使用第二掩模结构上的蚀刻掩模图案的部分作为掩模，第一掩模结构从第一区域中的间隔物之间选择性地移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物以及第二掩模图案，其包括在第二区域中具有第二掩模结构的相对的侧壁间隔物。可以使用第一掩模图案作为掩模来对特征层进行图案化，以在第一区域上限定第一特征，并且使用第二掩模图案作为掩模来限定具有比第一特征宽的宽度的第二区域上的第二特征。

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