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1. 发明申请

US20170125116A1 NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE 有权
公开(公告)号：US20170125116A1
公开(公告)日：2017-05-04
申请号：US15340957
申请日：2016-11-01
申请人： Dongkyo SHIM , Sang-Soo PARK
发明人： Dongkyo SHIM , Sang-Soo PARK
IPC分类号： G11C16/34 , G11C16/10 , G11C16/04 , G11C16/08 , G11C16/16 , G11C16/26
CPC分类号： G11C16/3445 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26
摘要： A nonvolatile memory device may include a memory cell array, an address decoder circuit, a page buffer circuit, and a control logic circuit. An erase operation includes iteratively performing an erase loop which includes an erase section where an erase voltage is applied to the memory cells of the selected memory block and an erase verification section where the memory cells of the selected memory block are verified using an erase verification voltage. If the memory cells of the selected memory block are determined as an erase pass in the erase verification section, the control logic circuit monitors the memory cells of the selected memory block. If the monitored result indicates that the memory cells of the selected memory block are at an abnormal state, the control logic circuit applies an extra erase voltage to the memory cells of the selected memory block.

2. 发明授权

US08934298B2 Nonvolatile memory device and related programming method 有权
标题翻译：非易失性存储器件及相关编程方法
公开(公告)号：US08934298B2
公开(公告)日：2015-01-13
申请号：US13600361
申请日：2012-08-31
申请人： Sang-Soo Park , Jae-Yong Jeong
发明人： Sang-Soo Park , Jae-Yong Jeong
IPC分类号： G11C11/34 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12
摘要： A nonvolatile memory device is programmed by performing a plurality of program loops each comprising sequentially applying first through n-th program pulses (n>1) to a selected wordline connected to a page of memory cells to be programmed, and incrementing each of the first through n-th program pulses prior to a next program loop, wherein the first through n-th program pulses are used to program selected memory cells to respective first through n-th program states, and during application of an i-th program pulse among the first through n-th program pulses (1
摘要翻译：通过执行多个程序循环来编程非易失性存储器件，每个程序循环包括顺序地将第n至第n个编程脉冲（n> 1）应用于连接到要被编程的存储器单元的页面的选定字线，并且将第一通过在下一个程序循环之前的第n个编程脉冲，其中第一到第n个编程脉冲用于将所选择的存储器单元编程到各自的第一至第n程序状态，并且在第i个编程脉冲之间施加第第一到第n个编程脉冲（1

3. 发明授权

US08724395B2 Nonvolatile memory device and related programming method 有权
标题翻译：非易失性存储器件及相关编程方法
公开(公告)号：US08724395B2
公开(公告)日：2014-05-13
申请号：US13483308
申请日：2012-05-30
申请人： Sang-Soo Park , Jae-Yong Jeong
发明人： Sang-Soo Park , Jae-Yong Jeong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3454
摘要： A nonvolatile memory device is programmed by performing a plurality of program loops each comprising applying a program voltage to a selected wordline to change a threshold voltage of a selected memory cell, and applying a verification voltage to the selected wordline to verify a program state of the selected memory cell. In each program loop, the nonvolatile memory device determines a program condition and increments the program voltage by an amount determined according to the program condition.
摘要翻译：通过执行多个程序循环来编程非易失性存储器件，每个程序循环包括对所选择的字线施加编程电压以改变所选择的存储单元的阈值电压，以及将验证电压施加到所选择的字线以验证选择的存储单元。在每个程序循环中，非易失性存储器件确定程序状态，并使程序电压递增根据程序条件确定的量。

4. 发明申请

US20130169399A1 THIN FILM-TYPE COIL COMPONENT AND METHOD OF FABRICATING THE SAME 有权
公开(公告)号：US20130169399A1
公开(公告)日：2013-07-04
申请号：US13417832
申请日：2012-03-12
申请人： Young Seuck YOO , Young Ghyu Ahn , Yong Suk Kim , Sung Kwon Wi , Sang Soo Park , Kang Heon Hur
发明人： Young Seuck YOO , Young Ghyu Ahn , Yong Suk Kim , Sung Kwon Wi , Sang Soo Park , Kang Heon Hur
IPC分类号： H01F27/28 , B05D5/12
CPC分类号： H01F27/2804 , H01F17/0013 , H01F27/29 , H01F41/042 , H01F2027/2809
摘要： There is provided a thin film-type coil component having a size equal to or less than 0806 and including a ceramic main body, external electrodes including a plurality of first external electrodes formed on one surface of the ceramic main body and a plurality of second external electrodes formed on the other surface facing one surface of the ceramic main body, and a coil unit including a plurality of coil layers stacked in the ceramic main body, thereby obtaining low direct current (DC) resistance.

5. 发明授权

US08351180B1 Multilayer ceramic capacitor 有权
标题翻译：多层陶瓷电容器
公开(公告)号：US08351180B1
公开(公告)日：2013-01-08
申请号：US13531237
申请日：2012-06-22
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/06
CPC分类号： H01G4/12 , H01G4/012 , H01G4/30
摘要： There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.
摘要翻译：提供了一种多层陶瓷电容器，包括：多层体，其中多个电介质层在厚度方向上堆叠; 以及形成在所述多层体内并且包括彼此相对设置的第一和第二内部电极的内部电极层; 其中MA1与CA1的比率（MA1 / CA1）在0.07和0.20之间，其中CA1表示在长度和厚度方向上取下的多层体的横截面中的多层体的面积，MA1表示第一边缘部分是沿着长度和厚度方向截取的第一边缘部分，第一边缘部分是多层体的一部分，除了第一电容形成部分之外，第一和第二内部电极在其中重叠厚度方向。

6. 发明授权

US08315034B2 Multilayer chip capacitor with improved equivalent series resistance 有权
标题翻译：具有改善等效串联电阻的多层片式电容器
公开(公告)号：US08315034B2
公开(公告)日：2012-11-20
申请号：US12245856
申请日：2008-10-06
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228 , H01G4/06 , H01G4/38
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes a capacitor body including a first capacitor part and a second capacitor part, first and second external electrodes respectively formed on first and second longer side faces of the capacitor body, and third and fourth external electrodes respectively formed on first and second shorter side faces of the capacitor body. The first capacitor part includes first and second internal electrodes of opposite polarity, and the second capacitor part includes third and fourth internal electrodes of opposite polarity. The first to fourth internal electrodes each have one lead. The first to fourth external electrodes are respectively connected to the leads of the first to fourth internal electrodes. A series resonance frequency of the first capacitor part is different from that of the second capacitor part. Equivalent series resistance (ESR1) of the first capacitor part and the equivalent series resistance (ESR2) of the second capacitor part satisfy ERS1≧20 mΩ and 0.7(ESR1)≦ESR2≦1.3(ESR1).
摘要翻译：多层片状电容器包括电容器本体，其包括第一电容器部分和第二电容器部分，分别形成在电容器主体的第一和第二长侧面上的第一和第二外部电极，以及分别形成在第一和第二电极部分上的第三和第四外部电极电容器主体的较短侧面。第一电容器部分包括具有相反极性的第一和第二内部电极，并且第二电容器部分包括具有相反极性的第三和第四内部电极。第一至第四内部电极各有一个引线。第一至第四外部电极分别连接到第一至第四内部电极的引线。第一电容器部分的串联谐振频率与第二电容器部分的串联谐振频率不同。第一电容器部分的等效串联电阻（ESR1）和第二电容器部分的等效串联电阻（ESR2）满足ERS1≥20m＆OHgr; 和0.7（ESR1）＆nlE; ESR2＆N1; 1.3（ESR1）。

7. 发明授权

US08184425B2 Multilayer capacitor 有权
标题翻译：多层电容器
公开(公告)号：US08184425B2
公开(公告)日：2012-05-22
申请号：US12238796
申请日：2008-09-26
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228 , H01G4/005 , H01G4/20
CPC分类号： H01G4/228
摘要： There is provided a multilayer capacitor including: a capacitor body where a plurality of dielectric layers are laminated, the capacitor body including first and second surfaces opposing each other in a laminated direction, wherein the first surface provides a mounting surface; a plurality of first and second inner electrodes; an inner connecting conductor; and a plurality of first and second outer electrodes formed on an outer surface of the body, wherein a corresponding one of the outer electrodes having identical polarity to the inner connecting conductor includes at least one outer terminal formed on the first surface of the body to connect to the inner connecting conductor, and at least one outer connecting conductor formed on the second surface of the body to connect a corresponding one of the inner electrodes of identical polarity to the inner connecting conductor.
摘要翻译：提供了一种层叠电容器，其包括：层叠多个电介质层的电容器体，所述电容器主体包括在层叠方向上彼此相对的第一和第二表面，其中所述第一表面提供安装表面; 多个第一和第二内部电极; 内连接导体; 以及形成在所述主体的外表面上的多个第一外部电极和第二外部电极，其中与所述内部连接导体具有相同极性的相应的外部电极包括形成在所述主体的所述第一表面上的至少一个外部端子，以连接内部连接导体和形成在主体的第二表面上的至少一个外部连接导体，以将相当极性的相应的一个内部电极与内部连接导体相连接。

8. 发明申请

US20120092090A1 COUPLING STRUCTURE FOR MULTI-LAYERED CHIP FILTER, AND MULTI-LAYERED CHIP FILTER WITH THE STRUCTURE 有权
标题翻译：多层芯片滤波器的耦合结构和结构的多层芯片滤波器
公开(公告)号：US20120092090A1
公开(公告)日：2012-04-19
申请号：US13109647
申请日：2011-05-17
申请人： Young Ghyu AHN , Dong Seok PARK , Sang Soo PARK , Sung Jin PARK , Young Sun PARK , Bong Sup LIM
发明人： Young Ghyu AHN , Dong Seok PARK , Sang Soo PARK , Sung Jin PARK , Young Sun PARK , Bong Sup LIM
IPC分类号： H01P1/203
CPC分类号： H01P1/20345 , H01P5/02
摘要： Disclosed herein are a coupling structure for a multi-layered chip filter capable of overcoming a limitation of an existing coupling by improving a coupling structure and a multi-layered chip filter with the structure.The coupling structure according to an exemplary embodiment of the present invention includes: at least two overlap portion patterns each overlapped with a pattern formed on a resonator layer stacked therewith to form at least two overlap areas spaced from each other; and a connecting portion pattern formed by connecting at least three linear lines having a predetermined length to each other to connect the at least two overlap portion patterns to each other.
摘要翻译：这里公开了一种用于通过改进耦合结构来克服现有耦合的限制的多层芯片滤波器的耦合结构和具有该结构的多层芯片滤波器。根据本发明的示例性实施例的耦合结构包括：至少两个重叠部分图案，每个重叠部分图案与形成在其上堆叠的谐振器层上的图案重叠以形成彼此间隔开的至少两个重叠区域; 以及通过将具有预定长度的至少三条线性线彼此连接而形成的连接部分图案，以将至少两个重叠部分图案彼此连接。

9. 发明授权

US07843702B2 Printed circuit board having embedded RF module power stage circuit 失效
标题翻译：具有嵌入式RF模块功率级电路的印刷电路板
公开(公告)号：US07843702B2
公开(公告)日：2010-11-30
申请号：US12437042
申请日：2009-05-07
申请人： Don Chul Choi , Jae Cheol Ju , Dong Hwan Lee , Sang Soo Park , Hee Soo Yoon
发明人： Don Chul Choi , Jae Cheol Ju , Dong Hwan Lee , Sang Soo Park , Hee Soo Yoon
IPC分类号： H05K1/18
CPC分类号： H05K1/023 , H01L24/24 , H01L24/82 , H01L2224/24226 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/0104 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/04941 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H05K1/0233 , H05K1/112 , H05K1/16 , H05K1/162 , H05K3/4611 , H05K2201/09309 , H05K2201/09454 , H05K2201/09718 , H05K2201/10022 , H05K2201/1003 , H01L2924/00
摘要： Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.
摘要翻译：这里公开了具有嵌入其中的RF模块功率级电路的印刷电路板。具体地说，本发明涉及一种具有嵌入其中的RF模块功率级电路的印刷电路板，其中在多层有线电路板的电源平面上限定或形成用于电阻器，焊道或电感器的端子焊盘，将电阻器，焊道或电感器连接到电源平面，并且电阻器，焊道或电感器通过使用通孔或通过嵌入电阻器，焊道或电感器而与去耦电容器并联连接垂直于电源平面，从而减小RF模块的尺寸并提高其性能。

10. 发明授权

US07817007B2 Laminated inductor 有权
标题翻译：层压电感
公开(公告)号：US07817007B2
公开(公告)日：2010-10-19
申请号：US12194935
申请日：2008-08-20
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hyeog Soo Shin , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hyeog Soo Shin , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F3/14 , H01F17/04
摘要： There is provided a laminated inductor including: a body where a plurality of magnetic layers are laminated; a coil part formed on the magnetic layers, the coil part including a plurality of conductor patterns and a plurality of conductive vias; first and second external electrodes formed on an outer surface of the body to connect to both ends of the coil part, respectively; and a non-magnetic conductor formed on at least one of the magnetic layers so as to relax magnetic saturation caused by direct current flowing through the coil part. The laminated inductor employs the non-magnetic conductor as a non-magnetic gap to be simplified in a manufacturing process and effectively improved in DC superposition characteristics.
摘要翻译：提供一种层叠电感器，包括：层叠有多个磁性层的主体; 形成在所述磁性层上的线圈部分，所述线圈部分包括多个导体图案和多个导电通孔; 第一外部电极和第二外部电极分别形成在主体的外表面上以连接到线圈部分的两端; 以及形成在至少一个磁性层上的非磁性导体，以便缓和由直流电流流过线圈部分的磁饱和。层叠电感器在制造工艺中使用非磁性导体作为非磁性间隙进行简化，并有效地改善了DC叠加特性。

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