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1. 发明申请

US20070180412A1 Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole 有权
标题翻译：使用系统故障率提高半导体集成电路器件产量的方法和系统
公开(公告)号：US20070180412A1
公开(公告)日：2007-08-02
申请号：US11698029
申请日：2007-01-26
申请人： Choel-hwyi Bae , Sang-deok Kwon , Min-geon Cho , Gwang-hyeon Baek
发明人： Choel-hwyi Bae , Sang-deok Kwon , Min-geon Cho , Gwang-hyeon Baek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of enhancing yield of semiconductor integrated circuit includes determining multiple experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, forming test patterns representing each of the experimental values on a wafer and calculating experimental value-based systematic fault rates from the test patterns; converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates, calculating a length of a side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values, and calculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the respective experimental values in the desired layout.
摘要翻译：提高半导体集成电路的产量的方法包括确定多个实验值，每个实验值对应于从孔的一侧到围绕孔的形状的相对侧的距离，形成表示每个实验值的测试图案并从测试模式中计算基于实验值的系统故障率; 将孔的实验值系统故障率转换为基于实验值的系统故障率，计算孔的侧面与形状的相对侧之间的距离对应于孔的一侧的长度每个实验值，并且使用每个单位孔长度的实验值系统故障率和针对所需布局中的各个实验值计算的孔的边的长度来计算孔的系统故障率。

2. 发明授权

US07703055B2 Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole 有权
标题翻译：使用系统故障率提高半导体集成电路器件产量的方法和系统
公开(公告)号：US07703055B2
公开(公告)日：2010-04-20
申请号：US11698029
申请日：2007-01-26
申请人： Choel-hwyi Bae , Sang-deok Kwon , Min-geon Cho , Gwang-hyeon Baek
发明人： Choel-hwyi Bae , Sang-deok Kwon , Min-geon Cho , Gwang-hyeon Baek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of enhancing yield of semiconductor integrated circuit includes determining multiple experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, forming test patterns representing each of the experimental values on a wafer and calculating experimental value-based systematic fault rates from the test patterns; converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates, calculating a length of a side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values, and calculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the respective experimental values in the desired layout.
摘要翻译：提高半导体集成电路的产量的方法包括确定多个实验值，每个实验值对应于从孔的一侧到围绕孔的形状的相对侧的距离，形成表示每个实验值的测试图案并从测试模式中计算基于实验值的系统故障率; 将孔的实验值系统故障率转换为基于实验值的系统故障率，计算孔的侧面与形状的相对侧之间的距离对应于孔的一侧的长度每个实验值，并且使用每个单位孔长度的实验值系统故障率和针对所需布局中的各个实验值计算的孔的边的长度来计算孔的系统故障率。

3. 发明授权

US07802210B2 Methods and systems for analyzing layouts of semiconductor integrated circuit devices 有权
标题翻译：分析半导体集成电路器件布局的方法和系统
公开(公告)号：US07802210B2
公开(公告)日：2010-09-21
申请号：US11654340
申请日：2007-01-17
申请人： Choel-Hwyi Bae , Gwang-Hyeon Baek , Min-Geon Cho
发明人： Choel-Hwyi Bae , Gwang-Hyeon Baek , Min-Geon Cho
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method of analyzing layouts of semiconductor integrated circuit devices. The method includes calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest; calculating area-based fault rates of the plurality of layouts of interest using the random fault rate, systematic fault rate, parametric fault rate, and area; and selecting layouts of interest to be corrected from among the plurality of layouts of interest using the area-based fault rates of the plurality of layouts of interest.
摘要翻译：公开了分析半导体集成电路器件的布局的方法。该方法包括计算随机故障率，系统故障率，参数故障率和感兴趣的多个布局的区域; 使用随机故障率，系统故障率，参数故障率和面积来计算多个感兴趣布局的基于区域的故障率; 以及使用感兴趣的多个布局的基于区域的故障率从感兴趣的多个布局中选择要校正的兴趣的布局。

4. 发明申请

US20070174800A1 Methods and systems for analyzing layouts of semiconductor integrated circuit devices 有权
标题翻译：分析半导体集成电路器件布局的方法和系统
公开(公告)号：US20070174800A1
公开(公告)日：2007-07-26
申请号：US11654340
申请日：2007-01-17
申请人： Choel-Hwyi Bae , Gwang-Hyeon Baek , Min-Geon Cho
发明人： Choel-Hwyi Bae , Gwang-Hyeon Baek , Min-Geon Cho
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method of analyzing layouts of semiconductor integrated circuit devices. The method includes calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest; calculating area-based fault rates of the plurality of layouts of interest using the random fault rate, systematic fault rate, parametric fault rate, and area; and selecting layouts of interest to be corrected from among the plurality of layouts of interest using the area-based fault rates of the plurality of layouts of interest.
摘要翻译：公开了分析半导体集成电路器件的布局的方法。该方法包括计算随机故障率，系统故障率，参数故障率和感兴趣的多个布局的区域; 使用随机故障率，系统故障率，参数故障率和面积来计算多个感兴趣布局的基于区域的故障率; 以及使用感兴趣的多个布局的基于区域的故障率从感兴趣的多个布局中选择要校正的兴趣的布局。

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