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1. 发明专利

ZA201901793B CONCRETE BLOCK CONSTRUCTION METHOD AND GUIDE MEMBER FOR INSTALLING CONCRETE BLOCK 未知
公开(公告)号：ZA201901793B
公开(公告)日：2021-08-25
申请号：ZA201901793
申请日：2019-03-22
申请人： SANG GI KIM
发明人： KIM SANG GI
摘要： The present invention relates to a concrete block construction method and a guide member for installing the concrete block, in which the concrete block can be placed at an accurate position considering positions of a lower concrete block and a concrete block positioned at a side during installing the concrete block. Therefore, construction of the concrete block according to the present invention can be accurate and a construction speed thereof can be drastically increased.

2. 发明专利

BR112019003690A2 método para construção de bloco de concreto, e, membro de guia 未知
公开(公告)号：BR112019003690A2
公开(公告)日：2019-06-04
申请号：BR112019003690
申请日：2017-07-25
申请人： SANG GI KIM
发明人： SANG GI KIM
IPC分类号： E02B3/04 , E02D23/00 , E02D25/00
摘要： a presente invenção permite que um bloco de concreto seja facilmente assentado, durante instalação do bloco de concreto, em uma posição precisa que se ajusta às posições de um bloco de concreto em uma parte inferior do mesmo e um bloco de concreto posicionado em um lado do mesmo, por meio disto permitindo a construção precisa do bloco de concreto e melhorando bastante a velocidade da construção.

3. 发明授权

US10422094B2 Concrete block construction method and guide member for installing concrete block 有权
公开(公告)号：US10422094B2
公开(公告)日：2019-09-24
申请号：US16327074
申请日：2017-07-25
申请人： Sang Gi Kim
发明人： Sang Gi Kim
IPC分类号： E02B3/04 , E02D23/08 , E02D25/00 , E02D23/00
摘要： A concrete block construction method, including: manufacturing a plurality of concrete blocks each having a vertical guide hole formed in a vertical direction; preparing a guide member for installing the concrete blocks; forming a lower concrete block structure by installing at least one of the concrete blocks; placing the concrete block subject to be installed on the lower concrete block structure by inserting the installation guide pole into the vertical guide hole of the concrete block subject to be installed; and separating and recovering the guide member for installing the concrete block from the concrete block subject to be installed, after placing the concrete block subject to be installed.

4. 外观设计

USD620906S1 Television 有权
公开(公告)号：USD620906S1
公开(公告)日：2010-08-03
申请号：US29353737
申请日：2010-01-13
申请人： Hyung Yuel Kim , Jun Ki Kim , Sang Gi Kim , Mi Sun Park
设计人： Hyung Yuel Kim , Jun Ki Kim , Sang Gi Kim , Mi Sun Park

5. 发明申请

US20060109444A1 Exposure apparatus 有权
标题翻译：曝光装置
公开(公告)号：US20060109444A1
公开(公告)日：2006-05-25
申请号：US11249783
申请日：2005-10-13
申请人： Sang Gi Kim , Ju Wook Lee , Jong Moon Park , Seong Wook Yoo , Kun Sik Park , Yong Sun Yoon , Yoon Kyu Bae , Byung Won Lim , Jin Gun Koo , Boo Woo Kim
发明人： Sang Gi Kim , Ju Wook Lee , Jong Moon Park , Seong Wook Yoo , Kun Sik Park , Yong Sun Yoon , Yoon Kyu Bae , Byung Won Lim , Jin Gun Koo , Boo Woo Kim
IPC分类号： G03B27/54
CPC分类号： G03F7/70425
摘要： Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.
摘要翻译：提供了一种在半导体器件制造工艺中使用的晶片曝光装置，该曝光装置包括：用于反射从光源提供的光的反射镜; 用于改变从反射镜提供的光的路径的光路改变器; 首先将镜子安装在光路改换器的两侧，以改变光线的路径; 第二个镜子安装在材料的两侧以改变光线的路径; 和第三反射镜，其安装在掩模的两侧，以将由第一反射镜反射的光进入掩模，并将通过掩模的光进入第二反射镜，由此可以连续地将一个表面，两个表面或一个在晶片一次对准的状态下晶片的比表面。

6. 发明授权

US06759714B2 Semiconductor device having heat release structure using SOI substrate and fabrication method thereof 有权
标题翻译：具有使用SOI衬底的放热结构的半导体器件及其制造方法
公开(公告)号：US06759714B2
公开(公告)日：2004-07-06
申请号：US10322232
申请日：2002-12-17
申请人： Sang Gi Kim , Dae Woo Lee , Tae Moon Roh , Yil Suk Yang , II-Young Park , Byoung-Gon Yu , Jong Dae Kim
发明人： Sang Gi Kim , Dae Woo Lee , Tae Moon Roh , Yil Suk Yang , II-Young Park , Byoung-Gon Yu , Jong Dae Kim
IPC分类号： H01L2972
CPC分类号： H01L21/76289 , H01L21/84 , H01L23/367 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, aiid removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the tunneling region.
摘要翻译：提供半导体制造技术; 更具体地说，涉及具有使用绝缘体上硅（SOI）衬底的散热结构的半导体器件，以及制造半导体器件的方法。本研究的装置和方法提供了具有高散热结构和高放热结构的半导体器件及其制造方法。在研究中，通过在绝缘体上硅（SOI）衬底上形成集成电路，快速地通过隧道区域在衬底外部释放集成电路中产生的热和高频噪声，除去埋入集成电路下的绝缘层形成隧道区。当在隧道区域的上部和下部的表面上形成不均匀时，或者当具有优良导热性的空气或其它气体流入隧道区域时，可以进一步提高散热效率。

7. 发明授权

US06404011B2 Semiconductor power integrated circuit 有权
标题翻译：半导体电源集成电路
公开(公告)号：US06404011B2
公开(公告)日：2002-06-11
申请号：US09865004
申请日：2001-05-23
申请人： Jong-Dae Kim , Sang-Gi Kim , Jin-Gun Koo , Dae-Yong Kim
发明人： Jong-Dae Kim , Sang-Gi Kim , Jin-Gun Koo , Dae-Yong Kim
IPC分类号： H01L2976
CPC分类号： H01L21/84 , H01L21/76264 , H01L21/76283 , H01L27/1203
摘要： A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.
摘要翻译：一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。

8. 发明授权

US06211018B1 Method for fabricating high density trench gate type power device 有权
标题翻译：高密度沟槽栅型功率器件的制造方法
公开(公告)号：US06211018B1
公开(公告)日：2001-04-03
申请号：US09475281
申请日：1999-12-30
申请人： Kee Soo Nam , Sang Gi Kim , Tae Moon Roh , Jin Gun Koo
发明人： Kee Soo Nam , Sang Gi Kim , Tae Moon Roh , Jin Gun Koo
IPC分类号： H01L21336
CPC分类号： H01L29/66727 , H01L29/66348
摘要： A semiconductor technique is disclosed. Particularly a low voltage high current power device for use in a lithium ion secondary battery protecting circuit, a DC-DC converter and a motor is disclosed. Further, a method for fabricating a high density trench gate type power device is disclosed. That is, in the present invention, a trench gate mask is used for forming the well and/or source, and for this purpose, a side wall spacer is introduced. In this manner, the well and/or source is defined by using the trench gate mask, and therefore, 1 or 2 masking processes are skipped unlike the conventional process in which the well mask and the source mask are separately used. The decrease in the use of the masking process decreases the mask align errors, and therefore, the realization of a high density is rendered possible. Consequently, the on-resistance which is an important factor for the power device can be lowered.
摘要翻译：公开了半导体技术。特别地，公开了一种用于锂离子二次电池保护电路，DC-DC转换器和电动机的低压大电流功率器件。此外，公开了一种制造高密度沟槽栅型功率器件的方法。也就是说，在本发明中，沟槽栅极掩模用于形成阱和/或源，为此，引入了侧壁间隔物。以这种方式，通过使用沟槽栅极掩模来定义阱和/或源，因此与分开使用阱掩模和源掩模的常规工艺不同，跳过1或2个屏蔽处理。掩蔽过程的使用减少会降低掩模对准误差，因此可以实现高密度。因此，作为功率器件的重要因素的导通电阻可以降低。

9. 发明授权

US08629020B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08629020B2
公开(公告)日：2014-01-14
申请号：US13228479
申请日：2011-09-09
申请人： Sang Gi Kim , Jin-Gun Koo , Seong Wook Yoo , Jong-Moon Park , Jin Ho Lee , Kyoung Il Na , Yil Suk Yang , Jongdae Kim
发明人： Sang Gi Kim , Jin-Gun Koo , Seong Wook Yoo , Jong-Moon Park , Jin Ho Lee , Kyoung Il Na , Yil Suk Yang , Jongdae Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/2255 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.
摘要翻译：提供半导体器件及其制造方法。该方法包括：在第一导电类型的半导体衬底中形成沟槽; 在所述沟槽的侧壁和底表面上形成包含第二导电类型的掺杂剂的沟槽掺杂剂层; 通过将所述沟槽掺杂剂含量层中的掺杂剂扩散到所述半导体衬底中来形成掺杂区域; 并去除含沟槽掺杂剂层。

10. 发明申请

US20130326967A1 LARGE CONCRETE BLOCK FOR CRANE LIFTING, METHOD FOR MANUFACTURING SAME, AND METHOD FOR INSTALLING SAME 审中-公开
标题翻译：用于起重机的大型混凝土块，其制造方法及其安装方法
公开(公告)号：US20130326967A1
公开(公告)日：2013-12-12
申请号：US14000707
申请日：2012-02-21
申请人： Sang Gi Kim
发明人： Sang Gi Kim
IPC分类号： E02D5/00 , E04C1/00
CPC分类号： E02D5/00 , B66C1/666 , E04C1/00
摘要： Disclosed herein is a large concrete block for crane lifting. The large concrete block includes a large concrete block body (110) made of concrete, and a connection-wire-rope insert tube (120) made of synthetic resin. The connection-wire-rope insert tube is embedded at a medial portion thereof in the concrete block body in such a way that opposite ends of the connection-wire-rope insert tube are disposed at an upper surface of the concrete block body and oriented upwards. The present invention having the above construction can solve problems which have been caused in the conventional technique that uses a lifting eye member.
摘要翻译：这里公开了一种用于起重机提升的大型混凝土块。大型混凝土块包括由混凝土制成的大型混凝土块体（110）和由合成树脂制成的连接钢丝绳插入管（120）。连接钢丝绳插入管以其中间部分嵌入混凝土块体中，使得连接钢丝绳插入管的相对端设置在混凝土块体的上表面并向上取向。具有上述结构的本发明可以解决在使用起吊眼构件的传统技术中引起的问题。

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