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1. 发明申请

WO2007127294A9 EXHAUST SYSTEM 审中-公开
标题翻译：排气系统
公开(公告)号：WO2007127294A9
公开(公告)日：2009-02-12
申请号：PCT/US2007010112
申请日：2007-04-25
申请人： MITSUBISHI CABLE IND LTD , OSAKA RASENKAN KOGYO CO LTD , SPANSION LLC , SPANSION JAPAN LTD
IPC分类号： C23F1/00 , C23C16/44 , H01L21/205 , H01L21/22 , H01L21/306 , H01L21/3065 , H01L21/31
CPC分类号： C23C16/4412
摘要： An exhaust system includes: an exhaust pressure controller interposed in an exhaust passage and including: a pipe body including a side peripheral wall in which at least one port is formed; and a gas introduction wall for introducing an exhaust gas flowing from an upstream side of the pipe body so that the exhaust gas flows downstream without coming into direct contact with the port and vicinity thereof, one face of the gas introduction wall forming a pressure control path together with an inner face of the side peripheral wall while another face of the gas introduction wall forming an exhaust gas path along which the exhaust gas flows. The port communicates with the pressure control path, and the pressure control path communicates with the exhaust gas path at part downstream of the port.
摘要翻译：排气系统包括：置于排气通道中的排气压力控制器，包括：管体，其包括形成至少一个端口的侧壁; 以及气体引入壁，用于引入从管体的上游侧流出的排气，使得废气在下游流动而不与其端口及其附近直接接触，气体导入壁的一个面形成压力控制路径与侧壁的内表面一起，同时气体导入壁的另一面形成废气流过的排气路径。所述端口与所述压力控制路径连通，并且所述压力控制路径在所述端口的下游的部分与所述排气路径连通。

2. 发明申请

WO2006011222A8 SEMICONDUCTOR DEVICE AND WRITING METHOD 审中-公开
标题翻译：半导体器件和写入方法
公开(公告)号：WO2006011222A8
公开(公告)日：2006-03-16
申请号：PCT/JP2004010914
申请日：2004-07-30
申请人： SPANSION LLC , SPANSION JAPAN LTD , YAMADA SHIGEKAZU
发明人： YAMADA SHIGEKAZU
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C2216/14
摘要： A semiconductor device comprising a memory cell array including multi-valued memory cells each having a plurality of different threshold values; a first latch circuit for latching information in input information of multi-words; a second latch circuit for latching write information obtained by converting the information in the input information of the multi-words to information that are in accordance with the levels of the multi-valued memory cells; a write circuit for writing the information into the multi-valued memory cells for each group corresponding to the number of memory cells into which the information can be simultaneously written;and a control circuit for controlling the writing into the memory cell array. Thus, information are simultaneously written for each of the groups into which the input information of the multi-words are divided, so that the write time per unit word can be substantially shortened. In this way, during the writing into the multi-valued memory cells, even if programs and verifications must be repeated many times, the write time does not increase.
摘要翻译：一种半导体器件，包括具有多值存储单元的存储单元阵列，每个多值存储单元具有多个不同的阈值; 用于在多字输入信息中锁存信息的第一锁存电路; 第二锁存电路，用于锁存通过将多字的输入信息中的信息转换为与多值存储器单元的电平相对应的信息而获得的写入信息; 写入电路，用于将信息写入与可以同时写入信息的存储单元的数量相对应的每个组的多值存储单元;以及控制电路，用于控制对存储单元阵列的写入。因此，对于分割多字的输入信息的每个组同时写入信息，从而可以显着缩短每单位字的写入时间。以这种方式，在写入多值存储器单元期间，即使程序和验证必须重复多次，写入时间也不会增加。

3. 发明申请

WO2007127294A3 EXHAUST SYSTEM 审中-公开
标题翻译：排气系统
公开(公告)号：WO2007127294A3
公开(公告)日：2008-01-24
申请号：PCT/US2007010112
申请日：2007-04-25
申请人： MITSUBISHI CABLE IND LTD , OSAKA RASENKAN KOGYO CO LTD , SPANSION LLC , SPANSION JAPAN LTD
IPC分类号： C23F1/00 , C23C16/44 , H01L21/205 , H01L21/22 , H01L21/306 , H01L21/3065 , H01L21/31
CPC分类号： C23C16/4412
摘要： An exhaust system includes: an exhaust pressure controller interposed in an exhaust passage and including: a pipe body including a side peripheral wall in which at least one port is formed; and a gas introduction wall for introducing an exhaust gas flowing from an upstream side of the pipe body so that the exhaust gas flows downstream without coming into direct contact with the port and vicinity thereof, one face of the gas introduction wall forming a pressure control path together with an inner face of the side peripheral wall while another face of the gas introduction wall forming an exhaust gas path along which the exhaust gas flows. The port communicates with the pressure control path, and the pressure control path communicates with the exhaust gas path at part downstream of the port.
摘要翻译：排气系统包括：置于排气通道中的排气压力控制器，包括：管体，其包括形成至少一个端口的侧壁; 以及气体引入壁，用于引入从管体的上游侧流出的排气，使得废气在下游流动而不与其端口及其附近直接接触，气体导入壁的一个面形成压力控制路径与侧壁的内表面一起，同时气体导入壁的另一面形成废气流过的排气路径。所述端口与所述压力控制路径连通，并且所述压力控制路径在所述端口的下游的部分与所述排气路径连通。

4. 发明申请

WO2007043095A9 MEMORY DEVICE AND METHOD OF CONTROLLING MEMORY DEVICE 审中-公开
标题翻译：存储器件和控制存储器件的方法
公开(公告)号：WO2007043095A9
公开(公告)日：2007-05-31
申请号：PCT/JP2005018085
申请日：2005-09-30
申请人： SPANSION LLC , SPANSION JAPAN LTD , ARAKAWA HIDEKI , KAWAMOTO SATORU
发明人： ARAKAWA HIDEKI , KAWAMOTO SATORU
IPC分类号： G11C16/30
CPC分类号： G11C5/145
摘要： A bias voltage supplied to a memory cell array is selected between a boosted voltage boosted from an external voltage and a non-boosted voltage. In the period during which a DC-DC converter circuit supplies the boosted voltage boosted from the external voltage to an internal bias line for supplying the bias voltage to the memory cell array, a non-boosted voltage supply circuit for supplying the non-boosted voltage not exceeding the external voltage is put into the halt state. In the period during which the non-boosted voltage supply circuit supplies the non-boosted voltage to the internal bias line, the DC-DC converter circuit is put into the halt state. Sufficient power supply ability is ensured by using the DC-DC conversion circuit in the period during which the boosted voltage is supplied to the internal bias line, and the DC-DC converter circuit is maintained in the halt state in the period during which the non-boosted voltage is supplied to the internal bias line. In the period during which the boosted voltage is not required, the power consumption of the DC-DC converter circuit can be reduced.
摘要翻译：在从外部电压升压的升压电压和非升压电压之间选择提供给存储单元阵列的偏置电压。在DC-DC转换器电路将从外部电压升压的升压电压提供给用于将偏置电压提供给存储单元阵列的内部偏置线的期间内，提供非升压电压电路，不超过外部电压被置于停止状态。在非升压电压供给电路将非升压电压供给到内部偏置线的期间，DC-DC转换电路处于停止状态。在向内部偏置线提供升压电压的期间，通过使用DC-DC转换电路来确保足够的电力供给能力，并且DC-DC转换电路在非 - 所提供的电压被提供给内部偏置线。在不需要升压电压的期间，能够降低DC-DC转换电路的功耗。

5. 发明申请

WO2007127294A2 EXHAUST SYSTEM 审中-公开
标题翻译：排气系统
公开(公告)号：WO2007127294A2
公开(公告)日：2007-11-08
申请号：PCT/US2007/010112
申请日：2007-04-25
申请人： MITSUBISHI CABLE INDUSTRIES, LTD. , OSAKA RASENKAN KOGYO CO., LTD. , SPANSION LLC , SPANSION JAPAN LTD.
IPC分类号： G01N33/53
CPC分类号： C23C16/4412
摘要： An exhaust system includes: an exhaust pressure controller interposed in an exhaust passage and including: a pipe body including a side peripheral wall in which at least one port is formed; and a gas introduction wall for introducing an exhaust gas flowing from an upstream side of the pipe body so that the exhaust gas flows downstream without coming into direct contact with the port and vicinity thereof, one face of the gas introduction wall forming a pressure control path together with an inner face of the side peripheral wall while another face of the gas introduction wall forming an exhaust gas path along which the exhaust gas flows. The port communicates with the pressure control path, and the pressure control path communicates with the exhaust gas path at part downstream of the port.
摘要翻译：排气系统包括：置于排气通道中的排气压力控制器，包括：管体，其包括形成至少一个端口的侧壁; 以及气体引入壁，用于引入从管体的上游侧流出的排气，使得废气在下游流动而不与其端口及其附近直接接触，气体导入壁的一个面形成压力控制路径与侧壁的内表面一起，同时气体导入壁的另一面形成废气流过的排气路径。所述端口与所述压力控制路径连通，并且所述压力控制路径在所述端口的下游的部分与所述排气路径连通。

6. 发明专利

DE112004002836B4 Nichtflüchtige Halbleitervorrichtung und Verfahren zum automatischen Beheben eines Löschfehlers in der Halbleitervorrichtung 未知
公开(公告)号：DE112004002836B4
公开(公告)日：2014-11-27
申请号：DE112004002836
申请日：2004-04-21
申请人： SPANSION LLC N D GES D STAATES DELAWARE , SPANSION JAPAN LTD
发明人： SHINGO MASAKI
IPC分类号： G11C29/00 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/34
摘要： Halbleitervorrichtung mit: – elektrisch löschbaren/programmierbaren regulären Sektoren (61a, 61b, 61c, 61d); – mindestens einem elektrisch löschbaren/programmierbaren Reserve-Sektor (62) als potentieller Ersatz für die regulären Sektoren (61a, 61b, 61c, 61d); – einem Decoder (59), der einen der regulären Sektoren (61a, 61b, 61c, 61d) in Reaktion auf einen Löschbefehl auswählt; – einer Überwachungsschaltung (58), die eine Löschleistung eines von dem Decoder (59) ausgewählten regulären Sektors (61a, 61b, 61c, 61d) während des Löschens überwacht; und – einer Steuerschaltung (57), die automatisch den Reserve-Sektor (62) als Ersatz für den von dem Decoder (59) ausgewählten regulären Sektor (61a, 61b, 61c, 61d) auswählt, wenn der von dem Decoder (59) ausgewählte reguläre Sektor (61a, 61b, 61c, 61d) eine verringerte Löschleistung aufweist, – wobei sich der Reserve-Sektor (62) anfangs vor dem durch die Steuerschaltung (57) erfolgten Ausgewählt werden in einem Löschzustand befindet, – wobei die Überwachungsschaltung (58) einen Stromdetektor aufweist, der einen beim Löschen in dem von dem Decoder (59) ausgewählten regulären Sektor (61a, 61b, 61c, 61d) fließenden Leckstrom detektiert und – wobei der Leckstrom ein beim Löschen zwischen einer Wortleitung und einer Wanne des von dem Decoder (59) ausgewählten regulären Sektors (61a, 61b, 61c, 61d) fließender Strom ist.

7. 发明专利

GB201007572D0 Semiconductor device,address assignment method and verify method 未知
公开(公告)号：GB201007572D0
公开(公告)日：2010-06-23
申请号：GB201007572
申请日：2005-01-27
申请人： SPANSION LLC , SPANSION JAPAN LTD

8. 发明专利

GB2460213B Semiconductor device using memory cell array activation and erase information 未知
公开(公告)号：GB2460213B
公开(公告)日：2009-12-30
申请号：GB0917967
申请日：2004-05-12
申请人： SPANSION LLC , SPANSION JAPAN LTD
发明人： KIDO KAZUNARI , KURIHARA KAZUHIRO , YAMASHITA MINORU
IPC分类号： G11C16/22

9. 发明专利

GB2434674B Information setting method of nonvolatile storage device, and nonvolatile storage device 未知
公开(公告)号：GB2434674B
公开(公告)日：2009-12-16
申请号：GB0708999
申请日：2004-10-26
申请人： SPANSION LLC , SPANSION JAPAN LTD
发明人： NAGAO MITSUHIRO , KATO KENTA , KAWABATA SHOZO
IPC分类号： G11C16/06
摘要： A verify sense amplifier ( 19 ) reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit ( 21 ). Upon completion of rewriting, the comparator circuit ( 21 ) outputs a match signal MCH. A selector ( 23 ) outputs a decode signal STR(i) or SWP(i) indicative of a volatile data retaining unit ( 25 ), in correspondence with the non-volatile memory cell MC to be rewritten. According to a verify instruction signal PGV/ERV, the readout data read by the verify sense amplifier ( 19 ) is stored in the volatile data retaining unit ( 25 ). Control is performed with a match signal MCH instead of the verify instruction signal PGV/ERV, thereby storing the data in the volatile data retaining unit ( 25 ) upon completion of rewriting. Therefore, there is no need to re-read operational information from the non-volatile storage.

10. 发明专利

GB2429582B Carrier for stacked type semiconductor device and method of fabricating the same 未知
公开(公告)号：GB2429582B
公开(公告)日：2009-02-11
申请号：GB0622769
申请日：2004-05-11
申请人： SPANSION LLC , SPANSION JAPAN LTD
发明人： ONODERA MASANORI , KASAI JUNICHI , MEGURO KOUICHI , TANAKA JUNJI , SHINMA YASUHIRO , TAYA KOJI
IPC分类号： H01L25/10 , H01L21/48 , H01L23/02
摘要： A carrier for a stacked type semiconductor device includes a lower carrier having a first accommodating portion that accommodates a first semiconductor device, and an upper carrier having a second accommodating portion that accommodates a second semiconductor device stacked on the first semiconductor device so as to be placed in position on the first semiconductor device. It is thus possible to eliminate an additional device used for stacking the semiconductor device, and thereby reduce the cost.

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