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1. 发明申请

WO2011011007A1 NON-VOLATILE DATA-STORAGE LATCH 审中-公开
标题翻译：非易失性数据存储锁
公开(公告)号：WO2011011007A1
公开(公告)日：2011-01-27
申请号：PCT/US2009/051564
申请日：2009-07-23
申请人： HEWLETT-PACKARD DEVELOPMENT, COMPANY, L.P. , SNIDER, Gregory Stuart
发明人： SNIDER, Gregory Stuart
IPC分类号： G11C11/41 , G11C11/413 , G11C11/4193 , G11C5/14
CPC分类号： G11C13/0069 , G11C5/141 , G11C13/0007 , G11C14/00 , G11C19/00 , H03K3/45
摘要： One embodiments of the present invention is directed to a single-bit memory cell comprising a transistor-based bit latch having a data state and a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a previously-stored data state is retrieved and restored into the transistor-based bit latch by a restore operation. Another embodiment of the present invention is directed to a single-bit memory cell comprising a master-slave flip flop and a slave flip flop, and a power input, a memristor, a memory-cell power input, a first memory-cell clock input, a second memory-cell clock input, a memory-cell data input, a memory-cell data output, and two or more memory-cell control inputs.
摘要翻译：本发明的一个实施例涉及一种单位存储单元，其包括耦合到基于晶体管的位锁存器的具有数据状态的晶体管基锁存器和忆阻器，其中基于晶体管的位的数据状态通过存储操作存储锁存器，并且通过恢复操作从存储操作中检索先前存储的数据状态并将其恢复到基于晶体管的位锁存器中。本发明的另一实施例涉及一种包括主从触发器和从触发器的单位存储单元，以及电源输入，忆阻器，存储单元电源输入，第一存储单元时钟输入，第二存储单元时钟输入，存储单元数据输入，存储单元数据输出以及两个或多个存储单元控制输入。

2. 发明申请

WO2010144092A1 CAPACITIVE CROSSBAR ARRAYS 审中-公开
标题翻译：电容式横梁阵列
公开(公告)号：WO2010144092A1
公开(公告)日：2010-12-16
申请号：PCT/US2009/047164
申请日：2009-06-12
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , STRUKOV, Dmitri Borisovich , SNIDER, Gregory, S. , WILLIAMS, R. Stanley
发明人： STRUKOV, Dmitri Borisovich , SNIDER, Gregory, S. , WILLIAMS, R. Stanley
IPC分类号： G06F12/00
CPC分类号： G11C13/00 , G11C11/24 , G11C23/00 , G11C2207/066
摘要： A capacitive crossbar array (100) includes a first set of conductors (102) and a second set of conductors (104) which intersect to form crosspoints. A nonlinear capacitive device (106) is interposed between a first conductor (103) within the first set (102) and a second conductor (105) within the second set (104) at a crosspoint. The nonlinear capacitive device (106) is configured to store information which is accessible through said first conductor (103) and said second conductor (105). A method for utilizing a capacitive crossbar array (100) is also provided.
摘要翻译：电容纵横阵列（100）包括第一组导体（102）和第二组导体（104），其相交以形成交叉点。在第一组（102）内的第一导体（103）与第二组（104）内的第二导体（105）之间的交叉点处插入非线性电容性装置（106）。非线性电容性装置（106）被配置为存储可通过所述第一导体（103）和所述第二导体（105）访问的信息。还提供了一种用于使用电容式交叉开关阵列（100）的方法。

3. 发明申请

WO2008130645A2 COMPUTATIONAL NODES AND COMPUTATIONAL-NODE NETWORKS THAT INCLUDE DYNAMICAL-NANODEVICE CONNECTIONS 审中-公开
标题翻译：包含动态纳米级连接的计算节点和计算节点网络
公开(公告)号：WO2008130645A2
公开(公告)日：2008-10-30
申请号：PCT/US2008/005048
申请日：2008-04-18
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , SNIDER, Gregory, S.
发明人： SNIDER, Gregory, S.
IPC分类号： G06N3/02 , G06F15/18
CPC分类号： G06N3/063
摘要： Embodiments of the present invention employ dynamical, nanoscale devices, including memristive connections (1102) between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks (Figure 9) and neural networks (Figure 8). In many embodiments of the present invention, neuron-like computational devices (2002) are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires (1104, 1106) and memristive connections (1102) between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies.
摘要翻译：本发明的实施例采用动态纳米级装置，包括纳米线之间的忆阻连接（1102），用于构建并行分布式动态计算网络和系统，包括感知器网络（图9）和神经网络（图8）。在本发明的许多实施例中，神经元样计算设备（2002）由硅基微米级和/或亚微米级部件构成，并且通过包括纳米线（1104,1106）和忆阻连接（1102）的动态互连彼此互连。纳米线之间。在包括人类大脑在内的许多大规模并行，分布式的动态计算系统中，可能会有比神经元般的计算节点更多的互连。使用动态纳米级器件进行这些连接可以产生巨大的设计，空间，能量和计算效率。

4. 发明申请

WO2008121252A1 THREE-DIMENSIONAL CROSSBAR ARRAY SYSTEMS AND METHODS FOR WRITING INFORMATION TO AND READING INFORMATION STORED IN THREE-DIMENSIONAL CROSBAR ARRAY JUNCTIONS 审中-公开
标题翻译：三维十字架阵列系统和方法，用于写入信息并读取三维CROSBAR ARRAY JUNCTIONS中存储的信息
公开(公告)号：WO2008121252A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/003789
申请日：2008-03-21
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L. P. , WU, Wei , WILLIAMS, Stanley, R. , ROBINETT, Warren , SNIDER, Gregory , YU, Zhaoning , WANG, Shih-yuan , STEWART, Duncan
发明人： WU, Wei , WILLIAMS, Stanley, R. , ROBINETT, Warren , SNIDER, Gregory , YU, Zhaoning , WANG, Shih-yuan , STEWART, Duncan
IPC分类号： H01L27/108 , H01L27/04
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/00 , G11C13/0023 , G11C13/0033 , G11C2213/71 , G11C2213/79 , G11C2213/81 , H01L2924/0002 , Y10S977/762 , H01L2924/00
摘要： Various embodiments of the present invention are directed to three-dimensionall crossbar arrays (500, 1000). In one aspect of the present invention, a three-dimensional crossbar array (1000) includes a plurality of crossbar arrays (1102-1104), a first demultiplexer (1106), a second demultiplexer (1108), and a third demultiplexer (1110). Each crossbar array includes a first layer of nanowires (702-704), a second layer of nanowires (706-708) overlaying the first layer of nanowires, and a third layer of nanowires (710-712) overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.
摘要翻译：本发明的各种实施例涉及三维全横杆阵列（500,1000）。在本发明的一个方面中，三维交叉列阵列（1000）包括多个交叉列阵列（1102-1104），第一解复用器（1106），第二解复用器（1108）和第三解复用器（1110）。每个横杆阵列包括第一层纳米线（702-704），覆盖第一纳米线层的第二纳米线层（706-708）和覆盖第二纳米线层的第三纳米线层（710-712）。第一解复用器被配置为寻址每个交叉列阵列的纳米线的第一层中的纳米线，第二解复用器被配置为寻址每个交叉列阵列的第二纳米线层中的纳米线，并且第三解复用器被配置为向纳米线在每个交叉列阵列的第三层纳米线中。

5. 发明申请

WO2008076757A2 TOOL WITH NON-SLIP FEATURE OR FRICTION ASSEMBLY 审中-公开
标题翻译：具有非滑动特征或摩擦组件的工具
公开(公告)号：WO2008076757A2
公开(公告)日：2008-06-26
申请号：PCT/US2007/087240
申请日：2007-12-12
申请人： BLACK & DECKER INC. , HOBDEN, Robert , SNIDER, Gregory Scott , SERGYEYENKO, Oleksiy P.
发明人： HOBDEN, Robert , SNIDER, Gregory Scott , SERGYEYENKO, Oleksiy P.
IPC分类号： F16M11/00
CPC分类号： G01C9/02
摘要： Apparatuses are provided for various tools that incorporate materials with a high coefficient of friction and a low coefficient of friction. The materials with a low coefficient of friction may be mounted on a tool and have a perpendicular movement to the tool. This perpendicular movement may be implemented with a spring mechanism. The materials with a high coefficient of friction may be mounted on the tool in a fixed position. The tool may be pressed against a surface, first engaging the materials with a low coefficient of friction. The tool may freely move across the surface while the materials with a low coefficient of friction maintain contact with the surface. As the tool is continually pressed to the surface, the materials with a high coefficient of friction subsequently make contact with the surface, thereby causing the lateral movement of the tool with respect to the surface to be restricted and stabilized. An example of the tool may be a spirit or carpenter level.
摘要翻译：为具有高摩擦系数和低摩擦系数的各种工具提供设备。具有低摩擦系数的材料可以安装在工具上并且具有垂直于工具的运动。该垂直运动可以用弹簧机构来实现。具有高摩擦系数的材料可以以固定的位置安装在工具上。工具可以被压靠在表面上，首先以低摩擦系数接合材料。该工具可以自由地移动穿过表面，而具有低摩擦系数的材料保持与表面接触。随着工具被不断地压向表面，具有高摩擦系数的材料随后与表面接触，从而导致工具相对于表面的横向移动被限制和稳定。工具的一个例子可能是精神或木匠级别。

6. 发明申请

WO2007089522A1 MIXED-SCALE ELECTRONIC INTERFACE 审中-公开
标题翻译：混合尺寸电子接口
公开(公告)号：WO2007089522A1
公开(公告)日：2007-08-09
申请号：PCT/US2007/001988
申请日：2007-01-26
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L. P. , SNIDER, Gregory, S. , WILLIAMS, R., Stanley
发明人： SNIDER, Gregory, S. , WILLIAMS, R., Stanley
IPC分类号： G11C13/02
CPC分类号： H01L29/0665 , B82Y10/00 , G11C2213/81 , H01H1/0094 , H01L27/285 , H01L29/0673 , H01L29/0676 , H01L51/0591 , H01L51/0595
摘要： Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer (302, 308) and nanoscale features of a predominantly nanoscale layer (307, 313) . The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads (306, 312) densely interconnected by nanowire junctions (318) between sets of parallel, closely spaced nanowire bundles (314, 316) . The predominantly submicroscale or microscale layer indued pins (304, 310) positioned complementarily to the submicroscale or microscale pads (306, 312) in the predominantly nanoscale layer.
摘要翻译：本发明的实施例涉及包括在集成电路和电子设备中的混合比例电子接口，其提供主要是微尺度或亚微米级层（302,308）的微尺度特征之间的密集电互连和主要为纳米尺度的纳米尺度特征层（307,313）。在本发明的一个实施例中，主要是纳米尺度的层包括通过在平行的，紧密间隔的纳米线束（314,316）的组之间的纳米线结（318）密集地互连的亚微米级或微尺度焊盘（306,312）的镶嵌图案。主要是亚微米级或微尺度层包括与主要是纳米尺度层中的亚微米级或微尺度焊盘（306,312）互补定位的引脚（304,310）。

7. 发明申请

WO2008076791A3 TWIN LEVEL 审中-公开
公开(公告)号：WO2008076791A3
公开(公告)日：2008-06-26
申请号：PCT/US2007/087360
申请日：2007-12-13
申请人： BLACK & DECKER INC. , STRUTT, Benjamin John , SERGYEYENKO, Oleksly , SNIDER, Gregory Scott
发明人： STRUTT, Benjamin John , SERGYEYENKO, Oleksly , SNIDER, Gregory Scott
IPC分类号： G01C9/00 , G01C9/18
摘要： A twin level assembly (10) including two levels, wherein one of the two levels also contains an indicating device for performing a separate function, is disclosed The twin level assembly comprises a first level (12) and a second level (14) that is selectively receivable into the first level through an opening in an end cap and into a receptacle of the first level The second level is held in the first level by a retention mechanism The first level and the second level each have at least one bubble vial for visually displaying level indications, while the indicating device in the second level is a type of stud sensor, laser pointer, metal detector, wire detector, or a sonic measurement device.

8. 发明申请

WO2006096762A1 ANTISYMMETRIC NANOWIRE CROSSBARS 审中-公开
标题翻译：抗衡NANOWIRE CROSSBARS
公开(公告)号：WO2006096762A1
公开(公告)日：2006-09-14
申请号：PCT/US2006/008220
申请日：2006-03-07
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L. P. , SNIDER, Gregory S,
发明人： SNIDER, Gregory S,
IPC分类号： G11C13/02
CPC分类号： G11C13/0002 , B82Y10/00 , G11C2213/77 , G11C2213/81 , H04Q3/0004 , Y10S977/762
摘要： Various embodiments of the present invention are directed to antisymmetric nanowire-crossbar-circuit designs. Antisymmetric nanowire crossbars are composed, in certain embodiments of the present invention, of two or more microreigions that receive input signals (712, 801, 803) and two or more microregions that send output signals (713, 802, 804). Antisymmetric nanowire crossbars may include a nanowire-crossbar network (805) having signal paths that carry signals between (909) one or more of the microregions. The nano-crossbar network may also carry signals between external electronic devices and one or more of the microregions (903-907). Antisymmetric nanowire crossbars may additionally included two or more structures that supply voltage and ground.
摘要翻译：本发明的各种实施例涉及反对称纳米线 - 横向电路设计。在本发明的某些实施方案中，组合了两个或多个接收输入信号（712,801,803）和发送输出信号（713,802,804）的两个或多个微区域的微反应物的反对称纳米线交叉。反对称纳米线交叉杆可以包括纳米线交叉网络（805），其具有在（909）一个或多个微区域之间携带信号的信号路径。纳米交叉网络还可以在外部电子设备与一个或多个微区域之间携带信号（903-907）。反向对称纳米线交叉杆可以另外包括两个或更多个提供电压和接地的结构。

9. 发明申请

WO2008076791A2 TWIN LEVEL 审中-公开
标题翻译：双等级
公开(公告)号：WO2008076791A2
公开(公告)日：2008-06-26
申请号：PCT/US2007087360
申请日：2007-12-13
申请人： BLACK & DECKER INC , STRUTT BENJAMIN JOHN , SERGYEYENKO OLEKSLY , SNIDER GREGORY SCOTT
发明人： STRUTT BENJAMIN JOHN , SERGYEYENKO OLEKSLY , SNIDER GREGORY SCOTT
IPC分类号： G01C9/24 , G01C9/02
CPC分类号： G01C9/28
摘要： A twin level assembly including two levels, wherein one of the two levels also contains an indicating device for performing a separate function, is disclosed. The twin level assembly comprises a first level and a second level that is selectively receivable into the first level through an opening in an end cap and into a receptacle of the first level. The second level is held in the first level by a retention mechanism. The first level and the second level each have at least one bubble vial for visually displaying level indications, while the indicating device in the second level is a type of stud sensor, laser pointer, metal detector, wire detector, or a sonic measurement device.
摘要翻译：公开了一种包括两个级别的双级组件，其中两个级别中的一个还包含用于执行单独功能的指示装置。双层组件包括第一水平和第二水平，其可选择性地通过端盖中的开口并进入第一水平的容器进入第一水平。第二级由保留机制在第一级举行。第一级和第二级各自具有至少一个用于可视地显示电平指示的气泡瓶，而第二级中的指示装置是螺柱传感器，激光指示器，金属检测器，线检测器或声音测量装置的类型。

10. 发明申请

WO2006115968A3 ACTIVE INTERCONNECTS AND CONTROL POINTS IN INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路中的主动互连和控制点
公开(公告)号：WO2006115968A3
公开(公告)日：2007-08-16
申请号：PCT/US2006014856
申请日：2006-04-19
申请人： HEWLETT PACKARD DEVELOPMENT CO , WILLIAMS R STANLEY , KUEKES PHILLIP J , PERNER FREDERICK A , SNIDER GREGORY S , STEWART DUNCAN
发明人： WILLIAMS R STANLEY , KUEKES PHILLIP J , PERNER FREDERICK A , SNIDER GREGORY S , STEWART DUNCAN
IPC分类号： H01L21/66
CPC分类号： H05K7/1092 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In various embodiments of the present invention, tunable resistors (1102) are introduced at the interconnect layer of the integrated circuits (102) in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronics characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors (1102) included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains. In some cases, components and modules may be turned off, while, in other cases, components and modules may be turned on.
摘要翻译：在本发明的各种实施例中，可调谐电阻器（1102）被引入集成电路（102）的互连层，以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或配置后续制造的集成电路。例如，当某些内部组件（例如晶体管）由于制造缺陷而没有指定的电子特性时，根据本发明的实施例调整包括在集成电路的互连层中的可调电阻器（1102）的可变电阻可以用于调整内部电压和/或电平，以改善有缺陷的部件。在其他情况下，可调谐电阻器可以用作开关以配置集成电路部件，包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。在某些情况下，可能会关闭组件和模块，而在其他情况下，可能会打开组件和模块。

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