专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011146453A2 HETEROGENEOUS PHYSICAL MEDIA ATTACHMENT CIRCUITRY FOR INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：用于集成电路设备的异质物理介质连接电路
公开(公告)号：WO2011146453A2
公开(公告)日：2011-11-24
申请号：PCT/US2011/036773
申请日：2011-05-17
申请人： ALTERA CORPORATION , SHUMARAYEV, Sergey , KOK, Edwin Yew Fatt , SOH, Lip Kai , AW, Chee Hong , TAN, Tee Wee
发明人： SHUMARAYEV, Sergey , KOK, Edwin Yew Fatt , SOH, Lip Kai , AW, Chee Hong , TAN, Tee Wee
CPC分类号： H03L7/0805 , H03K19/1774 , H03K19/17744 , H03L7/0891 , H03L7/095
摘要： An integrated circuit includes physical media attachment ("PMA") circuitry that includes two different kinds of transceiver channels for serial data 5 signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively 10 usable as phase-locked loop ("PLL") circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.
摘要翻译：集成电路包括物理介质连接（“PMA”）电路，其包括用于串行数据5信号的两种不同类型的收发信道。一种收发信道用于收发相对低速的串行数据信号。另一种收发器通道适用于收发相对高速的串行数据信号。高速通道可选地10可用作锁相环（“PLL”）电路，用于提供其它高速和/或低速通道使用的时钟信号。低速通道也可以从单独的低速PLL电路获取时钟信号。

2. 发明申请

WO2009126267A2 PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION 审中-公开
标题翻译：针对10G以太网物理层解决方案优化的PLD架构
公开(公告)号：WO2009126267A2
公开(公告)日：2009-10-15
申请号：PCT/US2009/002188
申请日：2009-04-07
申请人： ALTERA CORPORATION , CHAN, Allen , SHUMARAYEV, Sergey , WONG, Wilson , DING, Weiqi
发明人： CHAN, Allen , SHUMARAYEV, Sergey , WONG, Wilson , DING, Weiqi
IPC分类号： H04L12/56
CPC分类号： H04L49/30 , H04L49/352
摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.
摘要翻译：集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10吉比特以太网（10GbE）收发器电路。可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

3. 发明申请

WO2011097442A1 CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES 审中-公开
标题翻译：时钟和数据恢复电路与自动调速和其他可能的特性
公开(公告)号：WO2011097442A1
公开(公告)日：2011-08-11
申请号：PCT/US2011/023693
申请日：2011-02-04
申请人： ALTERA CORPORATION , ASADUZZAMAN, Kazi , HOANG, Tim Tri , LAI, Tin H. , SHIH, Shou-Po , SHUMARAYEV, Sergey
发明人： ASADUZZAMAN, Kazi , HOANG, Tim Tri , LAI, Tin H. , SHIH, Shou-Po , SHUMARAYEV, Sergey
IPC分类号： H04L7/033 , H03L7/081
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/0898 , H03L7/099 , H03L7/183 , H04L7/0337
摘要： An integrated circuit ("IC") may include clock and data recovery ("CDR") circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.
摘要翻译：集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。这可以帮助IC支持采用自动速度协商的通信协议。

4. 发明申请

WO2010135097A3 CLOCK DISTRIBUTION TECHNIQUES FOR CHANNELS 审中-公开
公开(公告)号：WO2010135097A3
公开(公告)日：2010-11-25
申请号：PCT/US2010/034149
申请日：2010-05-08
申请人： ALTERA CORPORATION , HOANG, Tim Tri , TRAN, Thungoc , WONG, Wilson , SHUMARAYEV, Sergey
发明人： HOANG, Tim Tri , TRAN, Thungoc , WONG, Wilson , SHUMARAYEV, Sergey
IPC分类号： G06F1/10 , H03K19/177
摘要： A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.

5. 发明申请

WO2010033436A3 TECHNIQUES FOR GENERATING FRACTIONAL CLOCK SIGNALS 审中-公开
公开(公告)号：WO2010033436A3
公开(公告)日：2010-03-25
申请号：PCT/US2009/056753
申请日：2009-09-11
申请人： ALTERA CORPORATION , HOANG, Tim Tri , WONG, Wilson , SHUMARAYEV, Sergey
发明人： HOANG, Tim Tri , WONG, Wilson , SHUMARAYEV, Sergey
IPC分类号： H03L7/193 , H03L7/087
摘要： A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.

6. 发明申请

WO2012021332A3 CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING OSCILLOSCOPE, JITTER, AND/OR BIT-ERROR-RATE TESTER OPERATIONS 审中-公开
标题翻译：用于执行或促进OSCILLOSCOPE，JITTER和/或BIT错误率测试仪操作的集成电路的电路
公开(公告)号：WO2012021332A3
公开(公告)日：2012-04-12
申请号：PCT/US2011046239
申请日：2011-08-02
申请人： ALTERA CORP , LI PENG , SHIMANOUCHI MASASHI , SHUMARAYEV SERGEY , DING WEIQI , NARAYAN SRIRAM , CHOW DANIEL TUN LAI , PAN MINGDE
发明人： LI PENG , SHIMANOUCHI MASASHI , SHUMARAYEV SERGEY , DING WEIQI , NARAYAN SRIRAM , CHOW DANIEL TUN LAI , PAN MINGDE
IPC分类号： G01R31/303
CPC分类号： G01R31/31709 , G01R31/3171 , G01R31/31716 , H04L7/0337
摘要： An integrated circuit ("IC") may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate ("BER") analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.
摘要翻译：集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

7. 发明申请

WO2012021332A2 CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING OSCILLOSCOPE, JITTER, AND/OR BIT-ERROR-RATE TESTER OPERATIONS 审中-公开
标题翻译：用于执行或促进示波器，抖动和/或双误差率测试操作的集成电路的电路
公开(公告)号：WO2012021332A2
公开(公告)日：2012-02-16
申请号：PCT/US2011/046239
申请日：2011-08-02
申请人： ALTERA CORPORATION , LI, Peng , SHIMANOUCHI, Masashi , SHUMARAYEV, Sergey , DING, Weiqi , NARAYAN, Sriram , CHOW, Daniel Tun Lai , PAN, Mingde
发明人： LI, Peng , SHIMANOUCHI, Masashi , SHUMARAYEV, Sergey , DING, Weiqi , NARAYAN, Sriram , CHOW, Daniel Tun Lai , PAN, Mingde
IPC分类号： G01R31/303
CPC分类号： G01R31/31709 , G01R31/3171 , G01R31/31716 , H04L7/0337
摘要： An integrated circuit ("IC") may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate ("BER") analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.
摘要翻译：集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于传输具有可选抖动，可选噪声和/或可控可变驱动强度的串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这样的信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以在各种模式下工作，以执行或至少仿真示波器，误码率测试仪等的功能，用于测试有关抖动容限，噪声容限等的信号和电路。

8. 发明申请

WO2011119369A3 INTEGRATED CIRCUITS WITH CONFIGURABLE INDUCTORS 审中-公开
标题翻译：集成电路与可配置电感
公开(公告)号：WO2011119369A3
公开(公告)日：2011-11-24
申请号：PCT/US2011028465
申请日：2011-03-15
申请人： ALTERA CORP , DING WEIQI , SHUMARAYEV SERGEY , WONG WILSON , ATESOGLU ALI , IPPILI SHARAT BABU
发明人： DING WEIQI , SHUMARAYEV SERGEY , WONG WILSON , ATESOGLU ALI , IPPILI SHARAT BABU
IPC分类号： H03L7/099 , H01F17/00
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively coupled to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be coupled to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor air in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供带锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，电压控制振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲器电路。多个电感器中的选定的一个可以被主动地耦合到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以耦合到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲器电路中的相应输入晶体管空气。通过向振荡器电路中选定的一个提供高电压，并通过向其余振荡器电路提供地电压，在正常操作期间，可以选择一个振荡器电路。

9. 发明申请

WO2010135097A2 CLOCK DISTRIBUTION TECHNIQUES FOR CHANNELS 审中-公开
标题翻译：频道的时钟分配技术
公开(公告)号：WO2010135097A2
公开(公告)日：2010-11-25
申请号：PCT/US2010034149
申请日：2010-05-08
申请人： ALTERA CORP , HOANG TIM TRI , TRAN THUNGOC , WONG WILSON , SHUMARAYEV SERGEY
发明人： HOANG TIM TRI , TRAN THUNGOC , WONG WILSON , SHUMARAYEV SERGEY
IPC分类号： G06F1/10 , H03K19/177
CPC分类号： G06F1/10
摘要： A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.
摘要翻译：电路包括第一区域，第二区域和第三区域。第二区域包括产生时钟信号的锁定环路电路。锁定环电路接收与第一区域中产生的噪声隔离的电源电压。第三区域包括多个通道的四通道，并且时钟线耦合以将在第二区域中产生的至少一个时钟信号路由到每个四通道中的通道。第三个区域与电路中的第二个区域分开。

10. 发明申请

WO2010039232A2 AUTOMATIC CALIBRATION IN HIGH-SPEED SERIAL INTERFACE RECEIVER CIRCUITRY 审中-公开
标题翻译：高速串行接口电路中的自动校准
公开(公告)号：WO2010039232A2
公开(公告)日：2010-04-08
申请号：PCT/US2009005396
申请日：2009-09-29
申请人： ALTERA CORP , SHUMARAYEV SERGEY , WONG WILSON
发明人： SHUMARAYEV SERGEY , WONG WILSON
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04B3/04 , H04L1/205 , H04L25/03019
摘要： Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.
摘要翻译：用于接收串行数据信号（例如，高速串行数据信号）的电路包括用于产生串行数据信号的均衡版本的可调均衡器电路。均衡器电路可以包括可控可变DC增益和可控可变AC增益。该电路还可以包括用于分别产生指示均衡版本的眼睛的高度和宽度的第一和第二输出信号的眼高和眼宽度监视器电路。第一输出信号可以用于控制均衡器电路的DC增益，第二输出信号可以用于控制均衡器电路的AC增益。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式