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1. 发明申请

WO2011119369A3 INTEGRATED CIRCUITS WITH CONFIGURABLE INDUCTORS 审中-公开
标题翻译：集成电路与可配置电感
公开(公告)号：WO2011119369A3
公开(公告)日：2011-11-24
申请号：PCT/US2011028465
申请日：2011-03-15
申请人： ALTERA CORP , DING WEIQI , SHUMARAYEV SERGEY , WONG WILSON , ATESOGLU ALI , IPPILI SHARAT BABU
发明人： DING WEIQI , SHUMARAYEV SERGEY , WONG WILSON , ATESOGLU ALI , IPPILI SHARAT BABU
IPC分类号： H03L7/099 , H01F17/00
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively coupled to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be coupled to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor air in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供带锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，电压控制振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲器电路。多个电感器中的选定的一个可以被主动地耦合到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以耦合到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲器电路中的相应输入晶体管空气。通过向振荡器电路中选定的一个提供高电压，并通过向其余振荡器电路提供地电压，在正常操作期间，可以选择一个振荡器电路。

2. 发明申请

WO2009126267A3 PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION 审中-公开
标题翻译：针对10G以太网物理层解决方案优化的PLD架构
公开(公告)号：WO2009126267A3
公开(公告)日：2010-01-14
申请号：PCT/US2009002188
申请日：2009-04-07
申请人： ALTERA CORP , CHAN ALLEN , SHUMARAYEV SERGEY , WONG WILSON , DING WEIQI
发明人： CHAN ALLEN , SHUMARAYEV SERGEY , WONG WILSON , DING WEIQI
IPC分类号： H04L12/56
CPC分类号： H04L49/30 , H04L49/352
摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.
摘要翻译：集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10吉比特以太网（10GbE）收发器电路。可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

3. 发明申请

WO2010042447A3 TECHNIQUES FOR PROVIDING OPTION CONDUCTORS TO CONNECT COMPONENTS IN AN OSCILLATOR CIRCUIT 审中-公开
标题翻译：用于提供选项导体以连接振荡器电路中的组件的技术
公开(公告)号：WO2010042447A3
公开(公告)日：2010-07-22
申请号：PCT/US2009059569
申请日：2009-10-05
申请人： ALTERA CORP , SHUMARAYEV SERGEY , WONG WILSON , CHAN ALLEN , ATESOGLU ALI
发明人： SHUMARAYEV SERGEY , WONG WILSON , CHAN ALLEN , ATESOGLU ALI
IPC分类号： H03B5/08 , H03B5/12
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1243 , H03B5/1265 , H03B2201/011
摘要： An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.
摘要翻译：振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。振荡器电路还包括第二导电层中的变容二极管，电容器和可选导体。选择导体形成晶体管中的一个与电容器或变容二极管之间的至少一部分连接。

4. 发明申请

WO2012138509A3 TECHNIQUES FOR REDUCING DUTY CYCLE DISTORTION IN PERIODIC SIGNALS 审中-公开
标题翻译：减少周期性信号中占空比变化的技术
公开(公告)号：WO2012138509A3
公开(公告)日：2013-01-03
申请号：PCT/US2012030753
申请日：2012-03-27
申请人： ALTERA CORP , DING WEIQI , SHUMARAYEV SERGEY , WONG WILSON , HOANG TIM TRI , KE YANJING
发明人： DING WEIQI , SHUMARAYEV SERGEY , WONG WILSON , HOANG TIM TRI , KE YANJING
IPC分类号： H04B1/04 , H03L7/00
CPC分类号： H03K5/1565 , H03K3/017 , H03K5/12 , H03M9/00
摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.
摘要翻译：发射机电路可操作以响应于第一周期性信号提供输出信号。多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。采样器电路可操作以在第一操作阶段产生所选信号的第一采样。采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

5. 发明申请

WO2010135097A2 CLOCK DISTRIBUTION TECHNIQUES FOR CHANNELS 审中-公开
标题翻译：频道的时钟分配技术
公开(公告)号：WO2010135097A2
公开(公告)日：2010-11-25
申请号：PCT/US2010034149
申请日：2010-05-08
申请人： ALTERA CORP , HOANG TIM TRI , TRAN THUNGOC , WONG WILSON , SHUMARAYEV SERGEY
发明人： HOANG TIM TRI , TRAN THUNGOC , WONG WILSON , SHUMARAYEV SERGEY
IPC分类号： G06F1/10 , H03K19/177
CPC分类号： G06F1/10
摘要： A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.
摘要翻译：电路包括第一区域，第二区域和第三区域。第二区域包括产生时钟信号的锁定环路电路。锁定环电路接收与第一区域中产生的噪声隔离的电源电压。第三区域包括多个通道的四通道，并且时钟线耦合以将在第二区域中产生的至少一个时钟信号路由到每个四通道中的通道。第三个区域与电路中的第二个区域分开。

6. 发明申请

WO2010039232A2 AUTOMATIC CALIBRATION IN HIGH-SPEED SERIAL INTERFACE RECEIVER CIRCUITRY 审中-公开
标题翻译：高速串行接口电路中的自动校准
公开(公告)号：WO2010039232A2
公开(公告)日：2010-04-08
申请号：PCT/US2009005396
申请日：2009-09-29
申请人： ALTERA CORP , SHUMARAYEV SERGEY , WONG WILSON
发明人： SHUMARAYEV SERGEY , WONG WILSON
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04B3/04 , H04L1/205 , H04L25/03019
摘要： Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.
摘要翻译：用于接收串行数据信号（例如，高速串行数据信号）的电路包括用于产生串行数据信号的均衡版本的可调均衡器电路。均衡器电路可以包括可控可变DC增益和可控可变AC增益。该电路还可以包括用于分别产生指示均衡版本的眼睛的高度和宽度的第一和第二输出信号的眼高和眼宽度监视器电路。第一输出信号可以用于控制均衡器电路的DC增益，第二输出信号可以用于控制均衡器电路的AC增益。

7. 发明申请

WO2010051244A2 METHOD TO DIGITIZE ANALOG SIGNALS IN A SYSTEM UTILIZING DYNAMIC ANALOG TEST MULTIPLEXER FOR DIAGNOSTICS 审中-公开
标题翻译：数字化模拟信号的方法利用动态模拟测试多路复用器进行诊断
公开(公告)号：WO2010051244A2
公开(公告)日：2010-05-06
申请号：PCT/US2009062028
申请日：2009-10-26
申请人： ALTERA CORP , WONG WILSON , CHAN ALLEN , SHUMARAYEV SERGEY
发明人： WONG WILSON , CHAN ALLEN , SHUMARAYEV SERGEY
IPC分类号： G01R31/28 , H03M1/12
CPC分类号： G01R31/3167
摘要： An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.
摘要翻译：介绍了一种能够监测模拟模块内部模拟电压的集成电路。该集成电路有一个模拟测试多路复用器（mux），其输入端连接到模拟模块内部感兴趣的模拟电压。模拟测试多路复用器将选定的模拟电压从模拟模块引导至模拟测试多路复用器的输出。该集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。集成电路还包括模数转换器，用于将来自模拟测试多路复用器的选定模拟电压转换为数字表示。

8. 发明申请

WO2010033436A2 TECHNIQUES FOR GENERATING FRACTIONAL CLOCK SIGNALS 审中-公开
标题翻译：产生分数时钟信号的技术
公开(公告)号：WO2010033436A2
公开(公告)日：2010-03-25
申请号：PCT/US2009056753
申请日：2009-09-11
申请人： ALTERA CORP , HOANG TIM TRI , WONG WILSON , SHUMARAYEV SERGEY
发明人： HOANG TIM TRI , WONG WILSON , SHUMARAYEV SERGEY
IPC分类号： H03L7/193 , H03L7/087
CPC分类号： H03L7/099 , H03L7/18
摘要： A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.
摘要翻译：一种电路包括相位检测电路，时钟信号生成电路，第一分频器和第二分频器。相位检测电路将输入时钟信号与反馈信号进行比较以生成控制信号。时钟信号产生电路响应于控制信号产生周期性输出信号。第一分频器将周期性输出信号的频率除以第一值以产生第一分频信号。第二分频器将周期性输出信号的频率除以第二值以产生第二分频信号。第一和第二分频信号在不同的时间间隔期间作为反馈信号被路由到相位检测电路。

9. 发明申请

WO2007019222A2 HIGH-SPEED SERIAL DATA RECEIVER ARCHITECTURE 审中-公开
标题翻译：高速串行数据接收机架构
公开(公告)号：WO2007019222A2
公开(公告)日：2007-02-15
申请号：PCT/US2006030248
申请日：2006-08-02
申请人： ALTERA CORP , TRAN THUNGOC M , SHUMARAYEV SERGEY YURYEVICH , MAANGAT SIMARDEEP , WONG WILSON , PATEL RAKESH
发明人： TRAN THUNGOC M , SHUMARAYEV SERGEY YURYEVICH , MAANGAT SIMARDEEP , WONG WILSON , PATEL RAKESH
IPC分类号： H04L25/03
CPC分类号： H04L1/243 , H04L25/03878
摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
摘要翻译：用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。接收器电路的控制的各个方面可以是可编程的。

10. 发明申请

WO2005107965A3 METHODS AND SYSTEMS FOR SORTING UNADDRESSED ITEMS 审中-公开
标题翻译：用于分类未经处理的物品的方法和系统
公开(公告)号：WO2005107965A3
公开(公告)日：2007-05-24
申请号：PCT/US2004032203
申请日：2004-09-30
申请人： US POSTAL SERVICE , MCDONALD GLENN EDWARD , WONG WILSON
发明人： MCDONALD GLENN EDWARD , WONG WILSON
IPC分类号： B07C5/00 , B07C3/00 , G06K9/00
CPC分类号： B07C3/00 , Y10S209/90
摘要： Systems and methods for sorting a plurality of unaddressed items may comprise receiving delivery point address data. Furthermore, systems and methods for sorting a plurality of unaddressed items may comprise sorting the plurality of unaddressed items based on the delivery point address data. The plurality of unaddressed items may be sorted in an order in which they are to be delivered within a delivery zone specified by the delivery point address data.
摘要翻译：用于排序多个未寻址物品的系统和方法可以包括接收递送点地址数据。此外，用于排序多个未寻址项目的系统和方法可以包括基于递送点地址数据对多个未寻址项目进行排序。多个未解决的项目可以按照它们在由递送点地址数据指定的递送区域内被递送的顺序进行排序。

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