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1. 发明申请

US20100252829A1 SEMICONDUCTOR DEVICE, CIRCUIT SUBSTRATE, ELECTRO-OPTIC DEVICE AND ELECTRONIC APPARATUS 失效
标题翻译：半导体器件，电路基板，电光器件和电子设备
公开(公告)号：US20100252829A1
公开(公告)日：2010-10-07
申请号：US12776667
申请日：2010-05-10
申请人： Shuichi TANAKA , Haruki ITO , Yasuhito ARUGA , Ryohei TAMURA , Michiyoshi TAKANO
发明人： Shuichi TANAKA , Haruki ITO , Yasuhito ARUGA , Ryohei TAMURA , Michiyoshi TAKANO
IPC分类号： H01L23/498 , H01L23/544
CPC分类号： G09G3/006 , H01L27/14601 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014
摘要： A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
摘要翻译：第一实施例中的半导体器件包括：形成在有源表面上的电极焊盘和树脂突起; 从所述电极焊盘的表面沉积到所述树脂突起的表面的导电膜; 树脂凸起与树脂突起形成并与导电膜形成。半导体器件通过树脂凸块电极导电地连接到相对的基板。测试电极由导电膜形成，该导电膜延伸并施加到穿过树脂突起的电极焊盘的相对侧。

2. 发明授权

US07757862B2 Semiconductor chip housing tray 失效
标题翻译：半导体芯片外壳托盘
公开(公告)号：US07757862B2
公开(公告)日：2010-07-20
申请号：US12171945
申请日：2008-07-11
申请人： Ryohei Tamura , Tomoyuki Shindo , Hironori Ota , Kazuo Yazawa
发明人： Ryohei Tamura , Tomoyuki Shindo , Hironori Ota , Kazuo Yazawa
IPC分类号： B65D85/00
CPC分类号： H01L21/67333
摘要： A semiconductor chip housing tray that is used in a state of being stacked in a plurality of stages and houses a plurality of semiconductor chips, includes: a base plate; a plurality of upper surface protruding parts provided to an upper surface of the base plate and dividing the upper surface of the base plate into a plurality of first semiconductor chip housing areas; and a plurality of under surface protruding parts provided to an under surface of the base plate and dividing the under surface of the base plate into a plurality of second semiconductor chip housing areas. In the semiconductor chip housing tray, a margin width of the first semiconductor chip housing areas with respect to the semiconductor chips is smaller than a margin width of the second semiconductor chip housing areas with respect to the semiconductor chips.
摘要翻译：一种半导体芯片外壳托盘，其以多个层叠的状态使用并容纳多个半导体芯片，包括：基板; 多个上表面突出部，设置在所述基板的上表面，并将所述基板的上表面分割成多个第一半导体芯片容纳区域; 以及设置在所述基板的下表面的多个下表面突出部，并且将所述基板的下表面分割成多个第二半导体芯片容纳区域。在半导体芯片外壳托盘中，相对于半导体芯片的第一半导体芯片容纳区域的边缘宽度小于第二半导体芯片容纳区域相对于半导体芯片的边缘宽度。

3. 发明授权

US07276792B2 Semiconductor device, circuit substrate, electro-optic device and electronic appliance 失效
标题翻译：半导体器件，电路基板，电光器件和电子设备
公开(公告)号：US07276792B2
公开(公告)日：2007-10-02
申请号：US11128848
申请日：2005-05-13
申请人： Shuichi Tanaka , Haruki Ito , Yasuhito Aruga , Ryohei Tamura , Michiyoshi Takano
发明人： Shuichi Tanaka , Haruki Ito , Yasuhito Aruga , Ryohei Tamura , Michiyoshi Takano
IPC分类号： H01L23/48
CPC分类号： G09G3/006 , H01L27/14601 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014
摘要： A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
摘要翻译：第一实施例中的半导体器件包括：形成在有源表面上的电极焊盘和树脂突起; 从所述电极焊盘的表面沉积到所述树脂突起的表面的导电膜; 树脂凸起与树脂突起形成并与导电膜形成。半导体器件通过树脂凸块电极导电地连接到相对的基板。测试电极由导电膜形成，该导电膜延伸并施加到穿过树脂突起的电极焊盘的相对侧。

4. 发明授权

US08292079B2 Semiconductor chip holding tray 有权
标题翻译：半导体芯片托盘
公开(公告)号：US08292079B2
公开(公告)日：2012-10-23
申请号：US12843268
申请日：2010-07-26
申请人： Ryohei Tamura
发明人： Ryohei Tamura
IPC分类号： B65D21/00 , B65D85/00 , B65D85/48 , B65D1/34
CPC分类号： H01L21/67333
摘要： A semiconductor chip holding tray, includes: a base substrate; a first projection provided on the front surface of the base substrate, and disposed on a short edge side of the perimeter of a holding area, has a depression; a first raised portion provided on the front surface, and is disposed on a long edge side of the perimeter; a triangular cross-section second projection provided on the rear surface of the base substrate, and is disposed on a short edge side of the perimeter of a holding area; and a second raised portion provided on the rear surface, and is disposed on a long edge side of the perimeter of the holding area. The tray is arranged such that when two trays are stacked the second projection is fitted in the depression of the first projection.
摘要翻译：一种半导体芯片保持托盘，包括：基底基板; 设置在基板的前表面上并设置在保持区域的周边的短边侧的第一突起具有凹陷部; 设置在前表面上的第一凸起部分，并设置在周边的长边侧; 设置在基底基板的后表面上的三角形横截面第二突起，并且设置在保持区域的周边的短边侧; 以及设置在后表面上的第二凸起部分，并且设置在保持区域的周边的长边侧。托盘被布置成使得当两个托盘堆叠时，第二突起装配在第一突起的凹部中。

5. 发明申请

US20080012130A1 SEMICONDUCTOR DEVICE, CIRCUIT SUBSTRATE, ELECTRO-OPTIC DEVICE AND ELECTRONIC APPLIANCE 失效
标题翻译：半导体器件，电路基板，电光器件及电子设备
公开(公告)号：US20080012130A1
公开(公告)日：2008-01-17
申请号：US11855391
申请日：2007-09-14
申请人： Shuichi TANAKA , Haruki ITO , Yasuhito ARUGA , Ryohei TAMURA , Michiyoshi TAKANO
发明人： Shuichi TANAKA , Haruki ITO , Yasuhito ARUGA , Ryohei TAMURA , Michiyoshi TAKANO
IPC分类号： H01L23/48
CPC分类号： G09G3/006 , H01L27/14601 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014
摘要： A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
摘要翻译：第一实施例中的半导体器件包括：形成在有源表面上的电极焊盘和树脂突起; 从所述电极焊盘的表面沉积到所述树脂突起的表面的导电膜; 树脂凸起与树脂突起形成并与导电膜形成。半导体器件通过树脂凸块电极导电地连接到相对的基板。测试电极由导电膜形成，该导电膜延伸并施加到穿过树脂突起的电极焊盘的相对侧。

6. 发明申请

US20110056862A1 SEMICONDUCTOR CHIP HOLDING TRAY 有权
标题翻译：半导体芯片托盘
公开(公告)号：US20110056862A1
公开(公告)日：2011-03-10
申请号：US12843268
申请日：2010-07-26
申请人： Ryohei Tamura
发明人： Ryohei Tamura
IPC分类号： B65D21/00
CPC分类号： H01L21/67333
摘要： A semiconductor chip holding tray, a plurality of which are used by being stacked one on another, which holds a plurality of semiconductor chips of a rectangular planar shape, includes: a base substrate; a first projection; a first raised portion; a triangular cross-section second projection; and a second raised portion, wherein when two semiconductor chip holding trays are stacked one on the other in such a way that the front surface of the base substrate is opposed to the rear surface of the base substrate, the holding area formed on the front surface of the base substrate and the holding area formed on the rear surface of the base substrate are aligned, the second projection is fitted in the depression of the first projection, and the first raised portion and second raised portion are not aligned.
摘要翻译：包括多个保持多个矩形平面形状的半导体芯片的半导体芯片保持托盘，其多个被彼此层叠使用，包括：基底; 第一个投影第一个凸起部分; 三角形横截面第二投影; 以及第二凸起部分，其中当两个半导体芯片保持托盘彼此堆叠成使得所述基底基板的前表面与所述基底基板的后表面相对的方式堆叠时，形成在所述前表面上的保持区域和形成在基底基板的后表面上的保持区域对准，第二突起嵌合在第一突起的凹部中，并且第一凸起部分和第二凸起部分不对准。

7. 发明授权

US07888799B2 Semiconductor device, circuit substrate, electro-optic device and electronic appliance 失效
标题翻译：半导体器件，电路基板，电光器件和电子设备
公开(公告)号：US07888799B2
公开(公告)日：2011-02-15
申请号：US12776667
申请日：2010-05-10
申请人： Shuichi Tanaka , Haruki Ito , Yasuhito Aruga , Ryohei Tamura , Michiyoshi Takano
发明人： Shuichi Tanaka , Haruki Ito , Yasuhito Aruga , Ryohei Tamura , Michiyoshi Takano
IPC分类号： H01L23/48
CPC分类号： G09G3/006 , H01L27/14601 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014
摘要： A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
摘要翻译：第一实施例中的半导体器件包括：形成在有源表面上的电极焊盘和树脂突起; 从所述电极焊盘的表面沉积到所述树脂突起的表面的导电膜; 树脂凸起与树脂突起形成并与导电膜形成。半导体器件通过树脂凸块电极导电地连接到相对的基板。测试电极由导电膜形成，该导电膜延伸并施加到穿过树脂突起的电极焊盘的相对侧。

8. 发明申请

US20050275115A1 Semiconductor device, circuit substrate, electro-optic device and electronic appliance 失效
标题翻译：半导体器件，电路基板，电光器件和电子设备
公开(公告)号：US20050275115A1
公开(公告)日：2005-12-15
申请号：US11128848
申请日：2005-05-13
申请人： Shuichi Tanaka , Haruki Ito , Yasuhito Aruga , Ryohei Tamura , Michiyoshi Takano
发明人： Shuichi Tanaka , Haruki Ito , Yasuhito Aruga , Ryohei Tamura , Michiyoshi Takano
IPC分类号： G02F1/1345 , G09G3/00 , H01L21/3205 , H01L21/60 , H01L23/52 , H01L27/146 , H01L29/40
CPC分类号： G09G3/006 , H01L27/14601 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014
摘要： A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
摘要翻译：第一实施例中的半导体器件包括：形成在有源表面上的电极焊盘和树脂突起; 从所述电极焊盘的表面沉积到所述树脂突起的表面的导电膜; 树脂凸起与树脂突起形成并与导电膜形成。半导体器件通过树脂凸块电极导电地连接到相对的基板。测试电极由导电膜形成，该导电膜延伸并施加到穿过树脂突起的电极焊盘的相对侧。

9. 发明授权

US07741712B2 Semiconductor device, circuit substrate, electro-optic device and electronic appliance 失效
标题翻译：半导体器件，电路基板，电光器件和电子设备
公开(公告)号：US07741712B2
公开(公告)日：2010-06-22
申请号：US11855391
申请日：2007-09-14
申请人： Shuichi Tanaka , Haruki Ito , Yasuhito Aruga , Ryohei Tamura , Michiyoshi Takano
发明人： Shuichi Tanaka , Haruki Ito , Yasuhito Aruga , Ryohei Tamura , Michiyoshi Takano
IPC分类号： H01L23/48
CPC分类号： G09G3/006 , H01L27/14601 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014
摘要： A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
摘要翻译：第一实施例中的半导体器件包括：形成在有源表面上的电极焊盘和树脂突起; 从所述电极焊盘的表面沉积到所述树脂突起的表面的导电膜; 树脂凸起与树脂突起形成并与导电膜形成。半导体器件通过树脂凸块电极导电地连接到相对的基板。测试电极由导电膜形成，该导电膜延伸并施加到穿过树脂突起的电极焊盘的相对侧。

10. 发明申请

US20090050519A1 SEMICONDUCTOR CHIP HOUSING TRAY 失效
标题翻译：半导体芯片住宅托盘
公开(公告)号：US20090050519A1
公开(公告)日：2009-02-26
申请号：US12171945
申请日：2008-07-11
申请人： Ryohei TAMURA , Tomoyuki SHINDO , Hironori OTA , Kazuo YAZAWA
发明人： Ryohei TAMURA , Tomoyuki SHINDO , Hironori OTA , Kazuo YAZAWA
IPC分类号： B65D85/00
CPC分类号： H01L21/67333
摘要： A semiconductor chip housing tray that is used in a state of being stacked in a plurality of stages and houses a plurality of semiconductor chips, includes: a base plate; a plurality of upper surface protruding parts provided to an upper surface of the base plate and dividing the upper surface of the base plate into a plurality of first semiconductor chip housing areas; and a plurality of under surface protruding parts provided to an under surface of the base plate and dividing the under surface of the base plate into a plurality of second semiconductor chip housing areas. In the semiconductor chip housing tray, a margin width of the first semiconductor chip housing areas with respect to the semiconductor chips is smaller than a margin width of the second semiconductor chip housing areas with respect to the semiconductor chips.
摘要翻译：一种半导体芯片外壳托盘，其以多个层叠的状态使用并容纳多个半导体芯片，包括：基板; 多个上表面突出部，设置在所述基板的上表面，并将所述基板的上表面分割成多个第一半导体芯片容纳区域; 以及设置在所述基板的下表面的多个下表面突出部，并且将所述基板的下表面分割成多个第二半导体芯片容纳区域。在半导体芯片外壳托盘中，相对于半导体芯片的第一半导体芯片容纳区域的边缘宽度小于第二半导体芯片容纳区域相对于半导体芯片的边缘宽度。

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