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1. 发明授权

US08367500B1 Method of forming self aligned contacts for a power MOSFET 失效
标题翻译：形成功率MOSFET自对准触点的方法
公开(公告)号：US08367500B1
公开(公告)日：2013-02-05
申请号：US10378766
申请日：2003-03-03
申请人： Robert Q. Xu , Jacek Korec
发明人： Robert Q. Xu , Jacek Korec
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L29/407 , H01L29/7813
摘要： A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.
摘要翻译：公开了一种用于为沟槽功率MOSFET提供自对准触点的方法。该方法包括：通过沉积在氧化物层上的氮化硅掩模蚀刻衬底中的沟槽，在沟槽的壁上形成栅极氧化层，施加多晶硅以填充沟槽并覆盖氮化硅掩模的表面从氮化硅掩模的表面去除多晶硅并施加光致抗蚀剂掩模以覆盖栅极总线的位置。该方法还包括凹陷形成在沟槽中的多晶硅塞，其位于有源区域中以在多晶硅插塞之上形成凹槽，在形成于有源区域的沟槽中形成的多晶硅插塞之上形成的绝缘体填充凹陷，施加第四张照片抗蚀剂掩模以限定在氮化物层中打开的接触窗口，并且选择性地蚀刻氮化硅膜并留下覆盖位于有源区域中的沟槽的平坦表面氧化物按钮。此外，使用自对准间隔物操作限定电接触沟槽，并且将第五光致抗蚀剂掩模施加到到达半导体器件有源区域的图案金属接触。

2. 发明授权

US06709930B2 Thicker oxide formation at the trench bottom by selective oxide deposition 有权
标题翻译：通过选择性氧化物沉积在沟槽底部形成更厚的氧化物
公开(公告)号：US06709930B2
公开(公告)日：2004-03-23
申请号：US10176570
申请日：2002-06-21
申请人： Ben Chan , Kam Hong Lui , Christiana Yue , Ronald Wong , David Chang , Frederick P. Giles , Kyle Terrill , Mohamed N. Darwish , Deva Pattanayak , Robert Q. Xu , Kuo-in Chen
发明人： Ben Chan , Kam Hong Lui , Christiana Yue , Ronald Wong , David Chang , Frederick P. Giles , Kyle Terrill , Mohamed N. Darwish , Deva Pattanayak , Robert Q. Xu , Kuo-in Chen
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/42368
摘要： A trench MOSFET is formed by creating a trench in a semiconductor substrate, then forming a barrier layer over a portion of the side wall of the trench. A thick insulating layer is deposited in the bottom of the trench. The barrier layer is selected such that the thick insulating layer deposits in the bottom of the trench at a faster rate than the thick insulating layer deposits on the barrier layer. Embodiments of the present invention avoid stress and reliability problems associated with thermal growth of insulating layers, and avoid problems with control of the shape and thickness of the thick insulating layer encountered when a thick insulating layer is deposited, then etched to the proper shape and thickness.
摘要翻译：通过在半导体衬底中形成沟槽，然后在沟槽的侧壁的一部分上形成阻挡层来形成沟槽MOSFET。在沟槽的底部沉积厚的绝缘层。选择阻挡层使得厚的绝缘层以比绝缘层沉积在阻挡层上更快的速率沉积在沟槽的底部。本发明的实施例避免了与绝缘层的热生长相关的应力和可靠性问题，并且避免了当沉积厚绝缘层时遇到的厚绝缘层的形状和厚度的控制问题，然后蚀刻到适当的形状和厚度。

3. 发明申请

US20140077287A1 BREAKDOWN VOLTAGE BLOCKING DEVICE 有权
标题翻译：断开电压闭锁装置
公开(公告)号：US20140077287A1
公开(公告)日：2014-03-20
申请号：US13622997
申请日：2012-09-19
申请人： Robert Q. Xu , Qufei Chen
发明人： Robert Q. Xu , Qufei Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/66356 , H01L29/407 , H01L29/4236 , H01L29/66143 , H01L29/66643 , H01L29/66666 , H01L29/7391 , H01L29/7828 , H01L29/7839 , H01L29/8613 , H01L29/8725
摘要： In one embodiment, a breakdown voltage blocking device can include an epitaxial region located above a substrate and a plurality of source trenches formed in the epitaxial region. Each source trench can include a dielectric layer surrounding a conductive region. The breakdown voltage blocking device can also include a contact region located in an upper surface of the epitaxial region along with a gate trench formed in the epitaxial region. The gate trench can include a dielectric layer that lines the sidewalls and bottom of the gate trench and a conductive region located between the dielectric layer. The breakdown voltage blocking device can include source metal located above the plurality of source trenches and the contact region. The breakdown voltage blocking device can include gate metal located above the gate trench.
摘要翻译：在一个实施例中，击穿电压阻挡装置可以包括位于衬底上方的外延区域和形成在外延区域中的多个源极沟槽。每个源沟槽可以包括围绕导电区域的介电层。击穿电压阻挡装置还可以包括位于外延区域的上表面中的接触区域以及形成在外延区域中的栅极沟槽。栅极沟槽可以包括在栅极沟槽的侧壁和底部以及位于介电层之间的导电区域的电介质层。击穿电压阻挡装置可以包括位于多个源极沟槽和接触区域上方的源极金属。击穿电压阻挡装置可以包括位于栅极沟槽上方的栅极金属。

4. 发明授权

US08629019B2 Method of forming self aligned contacts for a power MOSFET 有权
标题翻译：形成功率MOSFET自对准触点的方法
公开(公告)号：US08629019B2
公开(公告)日：2014-01-14
申请号：US10254385
申请日：2002-09-24
申请人： Robert Q. Xu , Jacek Korec
发明人： Robert Q. Xu , Jacek Korec
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L29/407 , H01L29/7813
摘要： A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.
摘要翻译：公开了一种用于为沟槽功率MOSFET提供自对准触点的方法。该方法包括：通过沉积在氧化物层上的氮化硅掩模蚀刻衬底中的沟槽，在沟槽的壁上形成栅极氧化层，施加多晶硅以填充沟槽并覆盖氮化硅掩模的表面从氮化硅掩模的表面去除多晶硅并施加光致抗蚀剂掩模以覆盖栅极总线的位置。该方法还包括凹陷形成在沟槽中的多晶硅插塞，其位于有源区域中，以在多晶硅插塞之上形成凹陷，在形成于有源区域的沟槽中形成的多晶硅插塞之上形成一个绝缘体，从而施加第四张照片抗蚀剂掩模以限定在氮化物层中打开的接触窗口，并且选择性地蚀刻氮化硅膜并留下覆盖位于有源区域中的沟槽的平坦的表面氧化物按钮。此外，使用自对准间隔物操作限定电接触沟槽，并且将第五光致抗蚀剂掩模施加到到达半导体器件有源区域的图案金属接触。

5. 发明授权

US08080459B2 Self aligned contact in a semiconductor device and method of fabricating the same 有权
标题翻译：半导体器件中的自对准接触及其制造方法
公开(公告)号：US08080459B2
公开(公告)日：2011-12-20
申请号：US10869382
申请日：2004-06-15
申请人： Robert Q. Xu
发明人： Robert Q. Xu
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L29/0878 , H01L29/404 , H01L29/407 , H01L29/4232 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7813
摘要： A method of fabricating a self-aligned contact in a semiconductor device, in accordance with one embodiment of the present invention, includes etching a trench in a core area and partially extending into a termination area of a substrate. A first oxide is grown on the substrate proximate the trench. A polysilicon layer is deposited in the core area and the termination area. The polysilicon layer is selectively etched to form a gate region in the core area portion of the trench. The etching of the polysilicon layer also forms a first portion of a gate interconnect region in the termination area portion of the trench and a second portion in the termination area outside of the trench.
摘要翻译：根据本发明的一个实施例的在半导体器件中制造自对准接触的方法包括蚀刻芯区域中的沟槽并且部分地延伸到衬底的端接区域中。在靠近沟槽的衬底上生长第一氧化物。多晶硅层沉积在核心区域和终止区域中。选择性地蚀刻多晶硅层以在沟槽的芯部区域形成栅极区域。多晶硅层的蚀刻还在沟槽的终端区域部分中形成栅极互连区域的第一部分，并且在沟槽外部的终止区域中形成第二部分。

6. 发明申请

US20110089486A1 SUPER-HIGH DENSITY TRENCH MOSFET 有权
标题翻译：超高密度TRENCH MOSFET
公开(公告)号：US20110089486A1
公开(公告)日：2011-04-21
申请号：US12788158
申请日：2010-05-26
申请人： Robert Q. Xu , Kuo-In Chen , Karl Lichtenberger , Sharon Shi , Qufei Chen , Kyle Terrill
发明人： Robert Q. Xu , Kuo-In Chen , Karl Lichtenberger , Sharon Shi , Qufei Chen , Kyle Terrill
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0638 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7811
摘要： A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.
摘要翻译：在一个实施例中，一种方法可以包括在垂直金属氧化物半导体场效应晶体管（MOSFET）的主体区域中形成多个沟槽。此外，该方法可以包括将角度注入源区域进入体区域。此外，电介质材料可以在多个沟槽内生长。栅极多晶硅可以沉积在多个沟槽内。此外，该方法可以包括化学机械抛光栅极多晶硅。该方法还可以包括蚀刻多个沟槽内的栅极多晶硅。

7. 发明授权

US07012005B2 Self-aligned differential oxidation in trenches by ion implantation 有权
公开(公告)号：US07012005B2
公开(公告)日：2006-03-14
申请号：US10180154
申请日：2002-06-25
申请人： Karl Lichtenberger , Frederick P. Giles , Christiana Yue , Kyle Terrill , Mohamed N. Darwish , Deva Pattanayak , Kam Hong Lui , Robert Q. Xu , Kuo-in Chen
发明人： Karl Lichtenberger , Frederick P. Giles , Christiana Yue , Kyle Terrill , Mohamed N. Darwish , Deva Pattanayak , Kam Hong Lui , Robert Q. Xu , Kuo-in Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26506 , H01L21/26586 , H01L21/28211 , H01L21/2822 , H01L29/0847 , H01L29/0878 , H01L29/42368
摘要： In accordance with the present invention, a trench MOSFET is formed by creating a trench in a semiconductor substrate. A portion of either a side wall of the trench or the bottom of the trench is implanted with an implant species. An insulating layer is then grown overlying the bottom and side wall of the trench. The implant species is selected such that the insulating layer grows more quickly on the bottom of the trench than on the side wall of the trench, resulting in a thicker insulating layer in the bottom of the trench than on the trench side walls.

8. 发明授权

US09431530B2 Super-high density trench MOSFET 有权
标题翻译：超高密度沟槽MOSFET
公开(公告)号：US09431530B2
公开(公告)日：2016-08-30
申请号：US12788158
申请日：2010-05-26
申请人： Robert Q. Xu , Kuo-In Chen , Karl Lichtenberger , Sharon Shi , Qufei Chen , Kyle Terrill
发明人： Robert Q. Xu , Kuo-In Chen , Karl Lichtenberger , Sharon Shi , Qufei Chen , Kyle Terrill
IPC分类号： H01L21/336 , H01L29/792 , H01L29/78 , H01L29/66 , H01L21/265 , H01L29/06 , H01L29/40 , H01L29/423
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0638 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7811
摘要： A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.
摘要翻译：在一个实施例中，一种方法可以包括在垂直金属氧化物半导体场效应晶体管（MOSFET）的主体区域中形成多个沟槽。此外，该方法可以包括将角度注入源区域进入体区域。此外，电介质材料可以在多个沟槽内生长。栅极多晶硅可以沉积在多个沟槽内。此外，该方法可以包括化学机械抛光栅极多晶硅。该方法还可以包括蚀刻多个沟槽内的栅极多晶硅。

9. 发明授权

US07642164B1 Method of forming self aligned contacts for a power MOSFET 有权
标题翻译：形成功率MOSFET自对准触点的方法
公开(公告)号：US07642164B1
公开(公告)日：2010-01-05
申请号：US10951831
申请日：2004-09-27
申请人： Robert Q. Xu , Jacek Korec
发明人： Robert Q. Xu , Jacek Korec
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L29/407 , H01L29/7813
摘要： A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.
摘要翻译：公开了一种用于为沟槽功率MOSFET提供自对准触点的方法。该方法包括：通过沉积在氧化物层上的氮化硅掩模蚀刻衬底中的沟槽，在沟槽的壁上形成栅极氧化层，施加多晶硅以填充沟槽并覆盖氮化硅掩模的表面从氮化硅掩模的表面去除多晶硅并施加光致抗蚀剂掩模以覆盖栅极总线的位置。该方法还包括凹陷形成在沟槽中的多晶硅插塞，其位于有源区域中，以在多晶硅插塞之上形成凹陷，在形成于有源区域的沟槽中形成的多晶硅插塞之上形成一个绝缘体，从而施加第四张照片抗蚀剂掩模以限定在氮化物层中打开的接触窗口，并且选择性地蚀刻氮化硅膜并留下覆盖位于有源区域中的沟槽的平坦的表面氧化物按钮。此外，使用自对准间隔物操作限定电接触沟槽，并且将第五光致抗蚀剂掩模施加到到达半导体器件有源区域的图案金属接触。

10. 发明授权

US06858471B1 Semiconductor substrate with trenches for reducing substrate resistance 失效
标题翻译：具有沟槽的半导体衬底，用于降低衬底电阻
公开(公告)号：US06858471B1
公开(公告)日：2005-02-22
申请号：US10247906
申请日：2002-09-20
申请人： Jacek Korec , Robert Q. Xu , Mohammed Kasem
发明人： Jacek Korec , Robert Q. Xu , Mohammed Kasem
IPC分类号： H01L21/44 , H01L29/06 , H01L29/45 , H01L29/739 , H01L29/78
CPC分类号： H01L29/456 , H01L24/32 , H01L29/0657 , H01L29/7395 , H01L29/7802 , H01L29/7813 , H01L2924/10155 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： In one embodiment of the present invention, a method for fabricating semiconductor devices comprises forming an active region about a front-side of a substrate. A plurality of trenches are then formed about a back-side of the substrate. A grid of banks separates the trenches. A conductive material is then applied to the back-side of the substrate. The trenches and the conductive material act to reduce the on-state resistance of the substrate and enhance thermal conductivity, while the grid of banks maintains the structural strength of the wafer.
摘要翻译：在本发明的一个实施例中，一种用于制造半导体器件的方法包括在基片的前侧形成有源区。然后围绕衬底的背面形成多个沟槽。银行网格分隔了沟渠。然后将导电材料施加到基板的背面。沟槽和导电材料用于降低衬底的导通电阻并提高热导率，而银栅格保持晶片的结构强度。

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