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1. 发明授权

US6154828A Method and apparatus for employing a cycle bit parallel executing instructions 失效
标题翻译：用于使用循环位指示并行执行指令的执行完成的方法和装置
公开(公告)号：US6154828A
公开(公告)日：2000-11-28
申请号：US072632
申请日：1993-06-03
申请人： Joseph Dominic Macri , Francis X. McKeen , Joel S. Emer , William Robert Grundmann , Robert P. Nix , David Arthur James Webb, Jr.
发明人： Joseph Dominic Macri , Francis X. McKeen , Joel S. Emer , William Robert Grundmann , Robert P. Nix , David Arthur James Webb, Jr.
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838
摘要： A method and apparatus including means for storing an executable file which includes a group of bits which define functional operations and cycle bits associated with each functional operation and means for completing a variable number of the functional operations in parallel during a single execution cycle in accordance with a state of the associated cycle bit. The method and apparatus eliminates the need for complex data dependency checking hardware and allows a minimum amount of control logic to complete execution of executable files. The method and apparatus further minimizes the necessity of adding null operations (NOPs) to executable files which reduces the amount of storage space necessary to store the executable files and allows executable files to be used on multiple hardware implementations and for register values to be used for multiple purposes during single execution cycles.
摘要翻译：一种方法和装置，包括用于存储可执行文件的装置，该可执行文件包括定义与每个功能操作相关联的功能操作和周期位的一组比特，以及用于在单个执行周期期间根据单个执行周期并行地完成可变数量的功能操作的装置相关联的周期位的状态。该方法和装置消除了对复杂数据依赖性检查硬件的需要，并允许最小量的控制逻辑来完成可执行文件的执行。该方法和装置进一步最小化了对可执行文件添加空操作（NOP）的必要性，这减少了存储可执行文件所需的存储空间量，并允许在多个硬件实现上使用可执行文件，并且使用用于在单个执行周期中有多个目的。

2. 发明授权

US5420990A Mechanism for enforcing the correct order of instruction execution 失效
标题翻译：执行指令执行顺序的机制
公开(公告)号：US5420990A
公开(公告)日：1995-05-30
申请号：US79494
申请日：1993-06-17
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3834 , G06F9/3842
摘要： An apparatus for enforcing that selected instructions are executed in a correct order, comprising a first content addressable memory for storing load addresses of data read from the memory by the selected instructions. The first content addressable memory comparing the store addresses with the load addresses of data to be written to the memory. The first content addressable memory generating a first signal, if one of the load addresses is identical to a subsequently compared one of the store addresses. The apparatus further including a second content addressable memory for storing and comparing states of the data read and written by the selected instructions. The second content addressable memory generating a second signal, if one of the stored states is identical to one of said compared states. The stored states including a program counter to repeat the execution of the selected instructions upon detecting the first and second signals.
摘要翻译：用于执行所选指令的装置以正确的顺序执行，包括用于存储由所选择的指令从存储器读取的数据的加载地址的第一内容可寻址存储器。第一内容可寻址存储器将存储地址与要写入存储器的数据的加载地址进行比较。所述第一内容可寻址存储器产生第一信号，如果所述加载地址之一与随后比较的一个所述存储地址相同。该装置还包括第二内容可寻址存储器，用于存储和比较由所选指令读和写的数据的状态。如果存储状态之一与所述比较状态之一相同，则第二内容可寻址存储器产生第二信号。所存储的状态包括在检测到第一和第二信号时重复所选指令的执行的程序计数器。

3. 发明授权

US06704861B1 Mechanism for executing computer instructions in parallel 失效
标题翻译：并行执行计算机指令的机制
公开(公告)号：US06704861B1
公开(公告)日：2004-03-09
申请号：US08752729
申请日：1996-11-19
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F938
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3865
摘要： A mechanism for executing computer instructions in parallel includes a compiler for generating and grouping instructions into a plurality of sets of instructions to be executed in parallel, each set having a unique identification. A computer system having a real state and a speculative state executes the sets in parallel, the computer system executing a particular set of instructions in the speculative state if the instructions of the particular set have dependencies which can not be resolved until the instructions are actually executed. The computer system generates speculative data while executing instructions in the speculative state. Logic circuits are provided to detect any exception conditions which occur while executing the particular set in the speculative state. If the particular set is subject to an exception condition, the instructions of the set are re-executed to resolve the exception condition, and to incorporate the speculative data in the real state of the computer system.
摘要翻译：用于并行执行计算机指令的机构包括：编译器，用于将指令生成和分组成并行执行的多组指令，每组具有唯一的标识。具有实际状态和推测状态的计算机系统并行地执行集合，如果特定集合的指令具有在实际执行指令之前无法解析的依赖关系，则计算机系统在推测状态下执行特定指令集。计算机系统在推测状态下执行指令时生成推测数据。提供逻辑电路以检测在推测状态下执行特定集合时发生的任何异常情况。如果特定集合受到异常条件的影响，则重新执行该集合的指令以解决异常条件，并将推测数据并入计算机系统的实际状态。

4. 发明授权

US5428807A Method and apparatus for propagating exception conditions of a computer system 失效
标题翻译：传播计算机系统异常情况的方法和装置
公开(公告)号：US5428807A
公开(公告)日：1995-06-27
申请号：US79498
申请日：1993-06-17
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowny
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowny
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3865 , G06F9/3834 , G06F9/3842 , G06F9/3863
摘要： There is provided a mechanism for propagating exception conditions in a computer system when instructions are subject to exception conditions. The apparatus includes a set of data registers for storing data manipulated by the instructions of the computer system, and a set of state registers for storing speculative states of data manipulated by the instructions, there being one state register associated with each data register. Furthermore, the apparatus includes a logic circuit, coupled to the set of state registers, for propagating the states from a source one of the state registers to a destination one of the state registers, if data stored in an associated source one of the data registers are used as a source for an associated destination one of data registers, and if data stored in the source data register were manipulated by a particular instruction subject to an exception condition.
摘要翻译：当指令受到异常条件的限制时，提供了一种在计算机系统中传播异常情况的机制。该装置包括一组数据寄存器，用于存储由计算机系统的指令操纵的数据，以及一组状态寄存器，用于存储由指令操纵的数据的推测状态，存在与每个数据寄存器相关联的一个状态寄存器。此外，该装置包括耦合到一组状态寄存器的逻辑电路，用于将状态从状态寄存器中的一个状态寄存器传播到状态寄存器的目的地寄存器，如果数据存储在相关源中的一个数据寄存器被用作相关联的目的地数据寄存器的源，并且如果存储在源数据寄存器中的数据被受异常条件的特定指令操纵。

5. 发明授权

US5421022A Apparatus and method for speculatively executing instructions in a computer system 失效
标题翻译：用于在计算机系统中推测执行指令的装置和方法
公开(公告)号：US5421022A
公开(公告)日：1995-05-30
申请号：US79309
申请日：1993-06-17
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/30 , G06F9/312 , G06F9/42 , G06F9/44
CPC分类号： G06F9/3865 , G06F9/3842
摘要： A compiler groups instructions into sets. The sets of instructions are related by data and control dependencies which are unresolvable by the compiler. Sets of instructions having unresolved dependencies are executed in a speculative state of the computer system under the assumption that an exception condition will not occur. However, if an exception condition does occur while executing a set of instructions in the speculative state, that exception condition is detected and the set of instructions is re-executed in a real state of the computer system to resolve the exception condition.
摘要翻译：编译器将指令分组成集合。指令集是由编译器无法解决的数据和控制依赖关系相关的。在具有未解决的依赖性的指令集在假定不发生异常条件的假设下在计算机系统的推测状态下执行。然而，如果在推测状态下执行一组指令时发生异常情况，则检测该异常条件，并且在计算机系统的实际状态中重新执行指令集以解决异常状况。

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