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1. 发明授权

US4811200A Multiple microprocessor watchdog system 失效
标题翻译：多处理器看门狗系统
公开(公告)号：US4811200A
公开(公告)日：1989-03-07
申请号：US049769
申请日：1987-05-12
申请人： David J. Wagner , Dean M. Picha , Stephen G. Oller , Robert J. Laping
发明人： David J. Wagner , Dean M. Picha , Stephen G. Oller , Robert J. Laping
IPC分类号： G06F11/00 , G06F11/14 , G06F11/32 , G06F11/28
CPC分类号： G06F11/0757 , G06F11/1415 , G06F11/32
摘要： A main microprocessor A (11) provides data to a display formatter microprocessor B (12) via a data bus (13). Microprocessor B provides data and latch (activity) pulses (34A) to a visual display (27) comprising a number of individual display devices (28-30) which are sequentially excited by data obtained from microprocessor B. An external activity detector (38), in response to an absence of the latch pulses of microprocessor B for a predetermined time, generates a reset signal (40) for resetting the microprocessor A. In response to being reset, microprocessor A provides an output control signal (at 20) which results in the resetting of the microprocessor B. If microprocessor B determines that microprocessor A is not properly providing data to it, microprocessor B will terminate generating the latch pulses (34A). The preceding configuration results in each of the microprocessors effectively monitoring the operation of the other microprocessor so as to insure proper system operation. Therefore, this system properly resets itself in response to any of a large number of different failures which may occur in either of the microprocessors, and this is accomplished with a minimum of additional hardware circuitry and software programming.
摘要翻译：主微处理器A（11）通过数据总线（13）向显示格式器微处理器B（12）提供数据。微处理器B将数据和锁存（活动）脉冲（34A）提供给包括由从微处理器B获得的数据顺序激励的多个单独显示设备（28-30）的视觉显示器（27）。外部活动检测器（38）响应于微处理器B的锁存脉冲不存在预定时间，产生用于复位微处理器A的复位信号（40）。响应于复位，微处理器A提供输出控制信号（在20），其结果在微处理器B的复位中。如果微处理器B确定微处理器A未正确提供数据，微处理器B将终止产生锁存脉冲（34A）。上述配置导致每个微处理器有效地监视其他微处理器的操作，以确保正确的系统操作。因此，该系统可以响应于任何微处理器中可能发生的大量不同故障中的任何一个而适当地重置自身，并且这通过最少的附加硬件电路和软件编程来实现。

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