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1. 发明授权

US08260040B2 Generation of a disparity result with low latency 有权
标题翻译：以低延迟生成视差结果
公开(公告)号：US08260040B2
公开(公告)日：2012-09-04
申请号：US13039248
申请日：2011-03-02
申请人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
发明人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
IPC分类号： G06K9/00
CPC分类号： G06T7/0075 , G01C11/06 , G06K9/32 , G06K9/6211 , G06T1/20 , G06T7/593 , G06T2207/10012 , H04N13/111 , H04N13/167 , H04N13/189 , H04N13/194 , H04N13/239 , H04N13/246 , H04N13/296 , H04N2013/0081
摘要： A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.
摘要翻译：描述了一种强大的，可扩展的和可重新配置的图像处理系统及其中的数据处理方法。这种具有环形拓扑，分布式存储器和宽带宽I / O的通用可重构引擎能够以实时速度解决实际应用。可重构图像处理系统可以被优化以有效地执行诸如实时视频和音频处理的专门计算。该可重构图像处理系统通过高计算密度，高存储带宽和高I / O带宽提供高性能。通常，可重构图像处理系统及其控制结构包括以局部环形配置布置的16个现场可编程门阵列（FPGA）和16个静态随机存取存储器（SRAM）的均匀阵列。可重构图像处理系统还包括PCI总线接口芯片，时钟控制芯片和数据通路芯片。它可以在单板中实现。它从其外部环境接收数据，计算对应关系，并使用各种后处理工业应用程序的对应计算结果。可重构图像处理系统通过使用非参数局部变换随后进行相关来确定对应关系。这些非参数局部变换包括人口普查和秩变换。其他实施例涉及对应，整改，左右一致性检查和感兴趣操作者的应用的组合。

2. 发明申请

US20110210851A1 Generation of a disparity result with low latency 有权
公开(公告)号：US20110210851A1
公开(公告)日：2011-09-01
申请号：US13039248
申请日：2011-03-02
申请人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
发明人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
IPC分类号： G08B21/00 , G06K9/36 , G06K9/00
CPC分类号： G06T7/0075 , G01C11/06 , G06K9/32 , G06K9/6211 , G06T1/20 , G06T7/593 , G06T2207/10012 , H04N13/111 , H04N13/167 , H04N13/189 , H04N13/194 , H04N13/239 , H04N13/246 , H04N13/296 , H04N2013/0081
摘要： A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.

3. 发明授权

US07925077B2 Generation of a disparity result with low latency 有权
标题翻译：以低延迟生成视差结果
公开(公告)号：US07925077B2
公开(公告)日：2011-04-12
申请号：US12362562
申请日：2009-01-30
申请人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
发明人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
IPC分类号： G06K9/00
CPC分类号： G06T7/0075 , G01C11/06 , G06K9/32 , G06K9/6211 , G06T1/20 , G06T7/593 , G06T2207/10012 , H04N13/111 , H04N13/167 , H04N13/189 , H04N13/194 , H04N13/239 , H04N13/246 , H04N13/296 , H04N2013/0081
摘要： A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.
摘要翻译：描述了一种强大的，可扩展的和可重新配置的图像处理系统及其中的数据处理方法。这种具有环形拓扑，分布式存储器和宽带宽I / O的通用可重构引擎能够以实时速度解决实际应用。可重构图像处理系统可以被优化以有效地执行诸如实时视频和音频处理的专门计算。该可重构图像处理系统通过高计算密度，高存储带宽和高I / O带宽提供高性能。通常，可重构图像处理系统及其控制结构包括以局部环形配置布置的16个现场可编程门阵列（FPGA）和16个静态随机存取存储器（SRAM）的均匀阵列。可重构图像处理系统还包括PCI总线接口芯片，时钟控制芯片和数据通路芯片。它可以在单板中实现。它从其外部环境接收数据，计算对应关系，并使用各种后处理工业应用程序的对应计算结果。可重构图像处理系统通过使用非参数局部变换随后进行相关来确定对应关系。这些非参数局部变换包括人口普查和秩变换。其他实施例涉及对应，整改，左右一致性检查和感兴趣操作者的应用的组合。

4. 发明授权

US07567702B2 Data processing system and method 有权
公开(公告)号：US07567702B2
公开(公告)日：2009-07-28
申请号：US11187613
申请日：2005-07-21
申请人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
发明人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
IPC分类号： G06T7/00 , G06T7/20 , G06T7/60
CPC分类号： G06T7/0075 , G01C11/06 , G06K9/32 , G06K9/6211 , G06T1/20 , G06T7/593 , G06T2207/10012 , H04N13/111 , H04N13/167 , H04N13/189 , H04N13/194 , H04N13/239 , H04N13/246 , H04N13/296 , H04N2013/0081
摘要： A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.

5. 发明申请

US20090136091A1 DATA PROCESSING SYSTEM AND METHOD 有权
标题翻译：数据处理系统和方法
公开(公告)号：US20090136091A1
公开(公告)日：2009-05-28
申请号：US12362562
申请日：2009-01-30
申请人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
发明人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
IPC分类号： G06K9/00
CPC分类号： G06T7/0075 , G01C11/06 , G06K9/32 , G06K9/6211 , G06T1/20 , G06T7/593 , G06T2207/10012 , H04N13/111 , H04N13/167 , H04N13/189 , H04N13/194 , H04N13/239 , H04N13/246 , H04N13/296 , H04N2013/0081
摘要： A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.
摘要翻译：描述了一种强大的，可扩展的和可重新配置的图像处理系统及其中的数据处理方法。这种具有环形拓扑，分布式存储器和宽带宽I / O的通用可重构引擎能够以实时速度解决实际应用。可重构图像处理系统可以被优化以有效地执行诸如实时视频和音频处理的专门计算。该可重构图像处理系统通过高计算密度，高存储带宽和高I / O带宽提供高性能。通常，可重构图像处理系统及其控制结构包括以局部环形配置布置的16个现场可编程门阵列（FPGA）和16个静态随机存取存储器（SRAM）的均匀阵列。可重构图像处理系统还包括PCI总线接口芯片，时钟控制芯片和数据通路芯片。它可以在单板中实现。它从其外部环境接收数据，计算对应关系，并使用各种后处理工业应用程序的对应计算结果。可重构图像处理系统通过使用非参数局部变换随后进行相关来确定对应关系。这些非参数局部变换包括人口普查和秩变换。其他实施例涉及对应，整改，左右一致性检查和感兴趣操作者的应用的组合。

6. 发明授权

US08639024B2 Generation of a disparity result with low latency 失效
标题翻译：以低延迟生成视差结果
公开(公告)号：US08639024B2
公开(公告)日：2014-01-28
申请号：US13563889
申请日：2012-08-01
申请人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
发明人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
IPC分类号： G06K9/00
CPC分类号： G06T7/0075 , G01C11/06 , G06K9/32 , G06K9/6211 , G06T1/20 , G06T7/593 , G06T2207/10012 , H04N13/111 , H04N13/167 , H04N13/189 , H04N13/194 , H04N13/239 , H04N13/246 , H04N13/296 , H04N2013/0081
摘要： A system for generating disparity results comprises an interface, a first memory, a second memory, and a processor. The interface is for receiving a first element of a first set of image data and a first element of a second set of image data. The first memory is for storing the first element of the first set of image data. The second memory is for storing the first element of the second set of image data. The processor is for generating a disparity result for a first element before all elements of the first data set and the second data set have been received. The disparity result is generated using a low latency image processing system that processes a plurality of elements of the first set of image data and a plurality of elements of the second set of image data.
摘要翻译：用于产生视差结果的系统包括接口，第一存储器，第二存储器和处理器。接口用于接收第一组图像数据的第一元素和第二组图像数据的第一元素。第一存储器用于存储第一组图像数据的第一元素。第二存储器用于存储第二组图像数据的第一元素。所述处理器用于在已经接收到所述第一数据集和所述第二数据集的所有元素之前生成第一元素的视差结果。使用处理第一组图像数据的多个元素和第二组图像数据的多个元素的低延迟图像处理系统来生成差异结果。

7. 发明申请

US20130101160A1 GENERATION OF A DISPARITY RESULT WITH LOW LATENCY 失效
标题翻译：缺乏结果的低产生的产生
公开(公告)号：US20130101160A1
公开(公告)日：2013-04-25
申请号：US13563889
申请日：2012-08-01
申请人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
发明人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
IPC分类号： G06T7/00
CPC分类号： G06T7/0075 , G01C11/06 , G06K9/32 , G06K9/6211 , G06T1/20 , G06T7/593 , G06T2207/10012 , H04N13/111 , H04N13/167 , H04N13/189 , H04N13/194 , H04N13/239 , H04N13/246 , H04N13/296 , H04N2013/0081
摘要： A system for generating disparity results comprises an interface, a first memory, a second memory, and a processor. The interface is for receiving a first element of a first set of image data and a first element of a second set of image data. The first memory is for storing the first element of the first set of image data. The second memory is for storing the first element of the second set of image data. The processor is for generating a disparity result for a first element before all elements of the first data set and the second data set have been received. The disparity result is generated using a low latency image processing system that processes a plurality of elements of the first set of image data and a plurality of elements of the second set of image data.
摘要翻译：用于产生视差结果的系统包括接口，第一存储器，第二存储器和处理器。接口用于接收第一组图像数据的第一元素和第二组图像数据的第一元素。第一存储器用于存储第一组图像数据的第一元素。第二存储器用于存储第二组图像数据的第一元素。所述处理器用于在已经接收到所述第一数据集和所述第二数据集的所有元素之前生成第一元素的视差结果。使用处理第一组图像数据的多个元素和第二组图像数据的多个元素的低延迟图像处理系统来生成视差结果。

8. 发明授权

US06456737B1 Data processing system and method 有权
标题翻译：数据处理系统及方法
公开(公告)号：US06456737B1
公开(公告)日：2002-09-24
申请号：US09641610
申请日：2000-08-17
申请人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
发明人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
IPC分类号： G06T120
CPC分类号： G06T7/0075 , G01C11/06 , G06K9/32 , G06K9/6211 , G06T1/20 , G06T7/593 , G06T2207/10012 , H04N13/111 , H04N13/167 , H04N13/189 , H04N13/194 , H04N13/239 , H04N13/246 , H04N13/296 , H04N2013/0081
摘要： A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.
摘要翻译：描述了一种强大的，可扩展的和可重新配置的图像处理系统及其中的数据处理方法。这种具有环形拓扑，分布式存储器和宽带宽I / O的通用可重构引擎能够以实时速度解决实际应用。可重构图像处理系统可以被优化以有效地执行诸如实时视频和音频处理的专门计算。该可重构图像处理系统通过高计算密度，高存储带宽和高I / O带宽提供高性能。通常，可重构图像处理系统及其控制结构包括以局部环形配置布置的16个现场可编程门阵列（FPGA）和16个静态随机存取存储器（SRAM）的均匀阵列。可重构图像处理系统还包括PCI总线接口芯片，时钟控制芯片和数据通路芯片。它可以在单板中实现。它从其外部环境接收数据，计算对应关系，并使用各种后处理工业应用程序的对应计算结果。可重构图像处理系统通过使用非参数局部变换随后进行相关来确定对应关系。这些非参数局部变换包括人口普查和秩变换。其他实施例涉及对应，整改，左右一致性检查和感兴趣操作者的应用的组合。

9. 发明授权

US06215898B1 Data processing system and method 失效
标题翻译：数据处理系统及方法
公开(公告)号：US06215898B1
公开(公告)日：2001-04-10
申请号：US08839767
申请日：1997-04-15
申请人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
发明人： John Iselin Woodfill , Henry Harlyn Baker , Brian Von Herzen , Robert Dale Alkire
IPC分类号： G06T700
CPC分类号： G06T7/0075 , G01C11/06 , G06K9/32 , G06K9/6211 , G06T1/20 , G06T7/593 , G06T2207/10012 , H04N13/111 , H04N13/167 , H04N13/189 , H04N13/194 , H04N13/239 , H04N13/246 , H04N13/296 , H04N2013/0081
摘要： A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.
摘要翻译：描述了一种强大的，可扩展的和可重新配置的图像处理系统及其中的数据处理方法。这种具有环形拓扑，分布式存储器和宽带宽I / O的通用可重构引擎能够以实时速度解决实际应用。可重构图像处理系统可以被优化以有效地执行诸如实时视频和音频处理的专门计算。该可重构图像处理系统通过高计算密度，高存储带宽和高I / O带宽提供高性能。通常，可重构图像处理系统及其控制结构包括以局部环形配置布置的16个现场可编程门阵列（FPGA）和16个静态随机存取存储器（SRAM）的均匀阵列。可重构图像处理系统还包括PCI总线接口芯片，时钟控制芯片和数据通路芯片。它可以在单板中实现。它从其外部环境接收数据，计算对应关系，并使用各种后处理工业应用程序的对应计算结果。可重构图像处理系统通过使用非参数局部变换随后进行相关来确定对应关系。这些非参数局部变换包括人口普查和秩变换。其他实施例涉及对应，整改，左右一致性检查和感兴趣操作者的应用的组合。

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