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1. 发明授权

US06956267B2 Semiconductor with a nitrided silicon gate oxide and method 有权
标题翻译：具有氮化硅栅氧化物的半导体和方法
公开(公告)号：US06956267B2
公开(公告)日：2005-10-18
申请号：US10783081
申请日：2004-02-19
申请人： Sunil V. Hattangady , Jaideep Mavoori , Che-Jen Hu , Rajesh B. Khamankar
发明人： Sunil V. Hattangady , Jaideep Mavoori , Che-Jen Hu , Rajesh B. Khamankar
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/51 , H01L29/76 , H01L29/78
CPC分类号： H01L29/518 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.
摘要翻译：制造晶体管的方法包括提供具有表面的半导体衬底，并在衬底的表面之外形成氮化物层。氮化物层被氧化以形成氮化层之下的包含氧化物层的氮化硅氧化物层。高K层沉积在氮化物层外面，导电层形成在高K层的外侧。对导电层，高K层和氮化硅氧化物层进行蚀刻和图案化以形成栅叠层。侧壁间隔物形成在与栅叠层相邻的半导体衬底的外侧，并且源极/漏极区形成在邻近侧壁间隔物的半导体衬底中。

2. 发明授权

US06326293B1 Formation of recessed polysilicon plugs using chemical-mechanical-polishing (CMP) and selective oxidation 有权
标题翻译：使用化学机械抛光（CMP）和选择性氧化形成凹陷多晶硅塞
公开(公告)号：US06326293B1
公开(公告)日：2001-12-04
申请号：US09216232
申请日：1998-12-18
申请人： Sung-Jen Fang , Mark R. Visokay , Rajesh B. Khamankar
发明人： Sung-Jen Fang , Mark R. Visokay , Rajesh B. Khamankar
IPC分类号： H01L2144
CPC分类号： H01L21/7684 , H01L21/76885
摘要： A plug is formed of polysilicon, or other oxidizable conductor. Chemical-mechanical polishing is performed, with a polish stop layer defining the top of the dielectric layer. The upper portion of the polysilicon is oxidized to a controlled depth, then the oxidized portion is removed by an etch, followed by removal of the polish stop layer. The plug thus formed protrudes a controllable distance above the surrounding dielectric, providing good contact to subsequent conductive layers.
摘要翻译：插头由多晶硅或其它可氧化导体形成。进行化学机械抛光，其中抛光停止层限定电介质层的顶部。多晶硅的上部被氧化成受控的深度，然后通过蚀刻去除氧化部分，随后除去抛光停止层。如此形成的插塞在周围的电介质上方突出可控的距离，提供与后续导电层的良好接触。

3. 发明授权

US06197653B1 Capacitor and memory structure and method 失效
标题翻译：电容和记忆结构及方法
公开(公告)号：US06197653B1
公开(公告)日：2001-03-06
申请号：US09049955
申请日：1998-03-27
申请人： Rajesh B. Khamankar , Darius L. Crenshaw , Rick L. Wise , Katherine Violette , Aditi D. Banerjee
发明人： Rajesh B. Khamankar , Darius L. Crenshaw , Rick L. Wise , Katherine Violette , Aditi D. Banerjee
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L27/10852 , H01L27/10855 , H01L28/84
摘要： A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.
摘要翻译：用于电容器的坚固的多晶硅电极具有高的表面积增强，薄层具有高成核密度加气相掺杂，这也增强了晶粒形状和无氧电介质形成。

4. 发明申请

US20090309140A1 IN-SITU CARBON DOPED e-SiGeCB STACK FOR MOS TRANSISTOR 有权
标题翻译：用于MOS晶体管的In-SITU碳掺杂e-SiGeCB堆叠
公开(公告)号：US20090309140A1
公开(公告)日：2009-12-17
申请号：US12482896
申请日：2009-06-11
申请人： Rajesh B. Khamankar , Haowen Bu , Douglas Tad Grider
发明人： Rajesh B. Khamankar , Haowen Bu , Douglas Tad Grider
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/823418 , H01L21/823814 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5'31019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.
摘要翻译：包含具有p沟道源极/漏极（PSD）区域的PMOS晶体管的集成电路，其包括含有Si-Ge，碳和硼的三层PSD堆叠。第一PSD层是Si-Ge，并且包括密度在5×1019到2×1020原子/ cm3之间的碳。第二PSD层是Si-Ge，并且包括密度在5×1019原子/ cm3至2×1020原子/ cm3之间的碳和密度高于5×1019原子/ cm3的硼。第三PSD层是硅或Si-Ge，包括密度高于5×1019原子/ cm3的硼并且基本上不含碳。在形成三层外延堆叠之后，第一PSD层的硼密度小于第二PSD层中硼密度的10％。一种在PSD凹槽中形成具有三层PSD堆叠的PMOS晶体管的集成电路的工艺。

5. 发明授权

US06716695B1 Semiconductor with a nitrided silicon gate oxide and method 有权
公开(公告)号：US06716695B1
公开(公告)日：2004-04-06
申请号：US10326188
申请日：2002-12-20
申请人： Sunil V. Hattangady , Jaideep Mavoori , Che-Jen Hu , Rajesh B. Khamankar
发明人： Sunil V. Hattangady , Jaideep Mavoori , Che-Jen Hu , Rajesh B. Khamankar
IPC分类号： H01L218242
CPC分类号： H01L29/518 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.

6. 发明授权

US08471307B2 In-situ carbon doped e-SiGeCB stack for MOS transistor 有权
标题翻译：用于MOS晶体管的原位碳掺杂e-SiGeCB堆叠
公开(公告)号：US08471307B2
公开(公告)日：2013-06-25
申请号：US12482896
申请日：2009-06-11
申请人： Rajesh B. Khamankar , Haowen Bu , Douglas Tad Grider
发明人： Rajesh B. Khamankar , Haowen Bu , Douglas Tad Grider
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L21/823418 , H01L21/823814 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5×1019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.
摘要翻译：包含具有p沟道源极/漏极（PSD）区域的PMOS晶体管的集成电路，其包括含有Si-Ge，碳和硼的三层PSD堆叠。第一PSD层是Si-Ge，并且包括密度在5×1019到2×1020原子/ cm3之间的碳。第二PSD层是Si-Ge，并且包括密度为5×1019原子/ cm3至2×1020原子/ cm3的碳和密度高于5×1019原子/ cm3的硼。第三PSD层是硅或Si-Ge，包括密度高于5×1019原子/ cm3的硼并且基本上不含碳。在形成三层外延堆叠之后，第一PSD层的硼密度小于第二PSD层中硼密度的10％。一种在PSD凹槽中形成具有三层PSD堆叠的PMOS晶体管的集成电路的工艺。

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