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1. 发明申请

WO2012139000A1 METHOD AND APPARATUS FOR OPTIMIZED EXECUTION USING RESOURCE UTILIZATION MAPS 审中-公开
标题翻译：使用资源利用方法优化执行的方法和装置
公开(公告)号：WO2012139000A1
公开(公告)日：2012-10-11
申请号：PCT/US2012/032523
申请日：2012-04-06
申请人： QUALCOMM INCORPORATED , RESHADI, Mehrdad, Mohammad, H. , SALAMAT, Babak , CASCAVAL, Gheorghe C. , FOWLER, Seth , ERMOLINSKIY, Andrey , RYCHLIK, Bohuslav
发明人： RESHADI, Mehrdad, Mohammad, H. , SALAMAT, Babak , CASCAVAL, Gheorghe C. , FOWLER, Seth , ERMOLINSKIY, Andrey , RYCHLIK, Bohuslav
IPC分类号： G06F9/50 , G06F3/048
CPC分类号： G06F9/5061 , G06F3/0481
摘要： Systems and methods enable displaying a graphical representation of system resource usage in a resource utilization map to inform users about system resource utilization by applications and processes running on a computing device. Users may provide inputs to enable the system to adjust resource allocations based on user preferences. This may enable users to improve the overall operational performance of the device consistent with their current personal preferences by identifying applications or processes of most or least interest so the device processor to prioritize system resources accordingly. Some aspects transmit resource allocation data based on such user input to a central server to enable community based resource allocation schemes. Community based resource allocation schemes may be transmitted to computing devices for use as default or preliminary resource allocations for particular applications, websites or device operating states.
摘要翻译：系统和方法使得能够在资源利用率图中显示系统资源使用的图形表示，以通知在计算设备上运行的应用和进程的系统资源利用。用户可以提供输入，以使系统能够根据用户偏好来调整资源分配。这可以使用户能够通过识别大多数或最不感兴趣的应用或过程来改善设备的整体操作性能，使其符合其当前的个人偏好，从而使设备处理器相应地优先考虑系统资源。一些方面将基于这样的用户输入的资源分配数据传送到中央服务器以实现基于社区的资源分配方案。基于社区的资源分配方案可以被传输到计算设备，以用作特定应用，网站或设备操作状态的默认或初始资源分配。

2. 发明申请

WO2011084330A3 SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED TRANSIENT DEADLINES 审中-公开
公开(公告)号：WO2011084330A3
公开(公告)日：2011-07-14
申请号：PCT/US2010/059542
申请日：2010-12-08
申请人： QUALCOMM Incorporated , THOMSON, Steven S. , RYCHLIK, Bohuslav , IRANLI, Ali , SUR, Sumit , GARGASH, Norman S.
发明人： THOMSON, Steven S. , RYCHLIK, Bohuslav , IRANLI, Ali , SUR, Sumit , GARGASH, Norman S.
IPC分类号： G06F1/32
摘要： A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget.

3. 发明申请

WO2010096263A2 ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS 审中-公开
标题翻译：多芯片系统中的原子操作凝聚技术
公开(公告)号：WO2010096263A2
公开(公告)日：2010-08-26
申请号：PCT/US2010/022886
申请日：2010-02-02
申请人： RAMBUS INC. , LIN, Qi , PENG, Liang , HAMPEL, Craig E. , SHEFFLER, Thomas J. , WOO, Steven C. , RYCHLIK, Bohuslav
发明人： LIN, Qi , PENG, Liang , HAMPEL, Craig E. , SHEFFLER, Thomas J. , WOO, Steven C. , RYCHLIK, Bohuslav
IPC分类号： G06F15/16 , G06F15/173 , G06F12/08 , G06F15/167
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/3834 , G06F12/0815
摘要： A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.
摘要翻译：高速缓存一致性协议在共享存储空间的多个处理器（或处理器内核）之间分配原子操作。当包括修改存储在共享存储空间中的数据的指令的原子操作被引导到不具有对与数据相关联的地址的控制的第一处理器时，第一处理器发送请求，该请求包括指令修改数据到第二个处理器。然后，已经控制地址的第二处理器修改数据。此外，第一个处理器可以立即继续执行另一条指令，而不是等待地址变为可用。

4. 发明申请

WO2007109631A2 REPRESENTING LOOP BRANCHES IN A BRANCH HISTORY REGISTER WITH MULTIPLE BITS 审中-公开
标题翻译：在分支机构历史记录中表示环路分支与多个位
公开(公告)号：WO2007109631A2
公开(公告)日：2007-09-27
申请号：PCT/US2007064331
申请日：2007-03-19
申请人： QUALCOMM INC , DIEFFENDERFER JAMES NORRIS , RYCHLIK BOHUSLAV
发明人： DIEFFENDERFER JAMES NORRIS , RYCHLIK BOHUSLAV
IPC分类号： G06F9/38
CPC分类号： G06F9/3848
摘要： In response to a property of a conditional branch instruction associated with a loop, such as a property indicating that the branch is a loop-ending branch, a count of the number of iterations of the loop is maintained, and a multi-bit value indicative of the loop iteration count is stored in a Branch History Register (BHR). In one embodiment, the multi-bit value may comprise the actual loop count, in which case the number of bits is variable. In another embodiment, the number of bits is fixed (e.g., two) and loop iteration counts are mapped to one of a fixed number of multi-bit values (e.g., four) by comparison to thresholds. Separate iteration counts may be maintained for nested loops, and a multi-bit value stored in the BHR may indicate a loop iteration count of only an inner loop, only the outer loop, or both.
摘要翻译：响应于与循环相关联的条件转移指令的属性，例如指示分支是循环结束分支的属性，维持循环的迭代次数的计数，并且指示多位值循环迭代计数存储在分支历史记录寄存器（BHR）中。在一个实施例中，多比特值可以包括实际循环计数，在这种情况下，比特数是可变的。在另一个实施例中，比特数是固定的（例如，两个），并且与阈值相比较，循环迭代计数被映射到固定数量的多比特值（例如，四）中的一个。对于嵌套循环可以保持单独的迭代计数，并且存储在BHR中的多位值可能仅表示内部循环，仅外部循环或两者的循环迭代计数。

5. 发明申请

WO2007048128A2 BACKING STORE BUFFER FOR THE REGISTER SAVE ENGINE OF A STACKED REGISTER FILE 审中-公开
标题翻译：用于注册的备份缓存保存堆叠寄存器文件的引擎
公开(公告)号：WO2007048128A2
公开(公告)日：2007-04-26
申请号：PCT/US2006/060128
申请日：2006-10-20
申请人： QUALCOMM INCORPORATED , RYCHLIK, Bohuslav
发明人： RYCHLIK, Bohuslav
IPC分类号： G06F9/30
CPC分类号： G06F9/30123 , G06F9/30116 , G06F9/30134
摘要： A Backing Store Buffer is interposed between a Physical Register File and the Backing Store in a stacked register file architecture. A Register Save Engine temporarily stores data from registers in the Physical Register File allocated to inactive procedures on-chip, freeing the registers to be re-allocated to new procedures. When the a procedures complete and returns control to a prior, inactive procedure, the Register Store Engine retrieves data associated with the inactive procedure from the Backing Store Buffer to registers in the Physical Register File, and the registers are re-allocated to the inactive procedure. The Register Save Engine saves data from the Backing Store Buffer to to the Backing Store, incurring the significant performance degradation and power consumption required for off-chip RAM access, only when the Backing Store Buffer is full and more data must be saved from the Physical Register File.
摘要翻译：一个备份存储缓冲区以一个堆栈寄存器文件体系结构插入在一个物理寄存器文件和备份存储之间。寄存器保存引擎临时将寄存器中的数据存储在物理寄存器文件中，分配给片上非活动程序，释放寄存器以重新分配给新程序。当一个过程完成并将控制返回到先前的不活动过程时，寄存器存储引擎将与非活动过程相关的数据从备份存储缓冲区中检索到寄存器中的寄存器中，并将寄存器重新分配给非活动过程。寄存器保存引擎将数据从备份存储缓冲区保存到备份存储区，仅当备份存储缓冲区已满并且必须从物理存储更多数据时才会导致片外RAM访问所需的显着性能下降和功耗注册文件。

6. 发明申请

WO2012094558A1 METHOD AND SYSTEM FOR MANAGING THERMAL POLICIES OF A PORTABLE COMPUTING DEVICE 审中-公开
标题翻译：用于管理便携式计算设备的热性能的方法和系统
公开(公告)号：WO2012094558A1
公开(公告)日：2012-07-12
申请号：PCT/US2012/020419
申请日：2012-01-06
申请人： QUALCOMM INCORPORATED , ANDERSON, Jon J. , NIEMANN, Jeffrey A. , RYCHLIK, Bohuslav , SUR, Sumit
发明人： ANDERSON, Jon J. , NIEMANN, Jeffrey A. , RYCHLIK, Bohuslav , SUR, Sumit
IPC分类号： G06F1/20
CPC分类号： G06F1/3296 , G06F1/203 , G06F1/206 , G06F1/324 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： A method and system for managing one or more thermal policies of a portable computing device (PCD) includes monitoring temperature of the portable computing device with internal thermal sensors and external thermal sensors. If a change in temperature has been detected by at least one thermal sensor, then a thermal policy manager may increase a frequency in which temperature readings are detected by the thermal sensors. The thermal policy manager may also determine if a current temperature of the portable computing device as detected by one or more of the thermal sensors falls within one or more predetermined thermal states. Each thermal state may be assigned a unique set of thermal mitigation techniques. Each set of thermal mitigation techniques may be different from one another. The sets of thermal mitigation techniques may differ according to quantity of techniques and impacts on performance of the PCD.
摘要翻译：用于管理便携式计算设备（PCD）的一个或多个热策略的方法和系统包括利用内部热传感器和外部热传感器监测便携式计算设备的温度。如果由至少一个热传感器检测到温度变化，则热策略管理器可以增加热传感器检测温度读数的频率。热策略管理器还可以确定由一个或多个热传感器检测到的便携式计算设备的当前温度是否落在一个或多个预定的热状态内。每个热状态可以分配一组独特的热缓解技术。每组热缓解技术可能彼此不同。根据技术数量和对PCD性能的影响，热减缓技术的组合可能不同。

7. 发明申请

WO2012054754A1 ARBITRATING BUS TRANSACTIONS ON A COMMUNICATIONS BUS BASED ON BUS DEVICE HEALTH INFORMATION AND RELATED POWER MANAGEMENT 审中-公开
标题翻译：根据总线设备健康信息和相关电源管理对通信总线进行总线交易
公开(公告)号：WO2012054754A1
公开(公告)日：2012-04-26
申请号：PCT/US2011/057142
申请日：2011-10-20
申请人： QUALCOMM INCORPORATED , DUROIU, Cristian , GANASAN, Jaya Prakash Subramaniam , CHAMARTY, Vinod , SCHAFFER, Mark Michael , STUBBS, Joshua H. , GIBSON, Robert N. , TIRI, Kris , KHAN, Moinul H. , RYCHLIK, Bohuslav , GADELRAB, Serag , BOOTH, Simon
发明人： DUROIU, Cristian , GANASAN, Jaya Prakash Subramaniam , CHAMARTY, Vinod , SCHAFFER, Mark Michael , STUBBS, Joshua H. , GIBSON, Robert N. , TIRI, Kris , KHAN, Moinul H. , RYCHLIK, Bohuslav , GADELRAB, Serag , BOOTH, Simon
IPC分类号： G06F13/362
CPC分类号： G06F13/362 , Y02D10/14
摘要： Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.
摘要翻译：公开了用于基于健康信息在通信总线上仲裁总线事务的设备，系统，方法和计算机可读介质。主设备的健康信息可用于调整主设备总线事务的优先级，以满足主设备的服务质量要求。在一个实施例中，总线互连被提供和配置为将总线事务从多个主设备中的任一个传送到耦合总线互连的从设备。总线互连还被配置为将多个主设备中的每一个的健康信息映射到虚拟优先级空间中。总线互连还被配置为将虚拟优先级空间转换为多个主设备中的每一个的物理优先级。总线互连还被配置为基于多个主设备的物理优先级来仲裁多个主设备的总线事务。

8. 发明申请

WO2011084336A1 SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH REDUCED FREQUENCY OSCILLATIONS 审中-公开
标题翻译：用减少频率振荡控制中央处理单元功率的系统和方法
公开(公告)号：WO2011084336A1
公开(公告)日：2011-07-14
申请号：PCT/US2010/059562
申请日：2010-12-08
申请人： QUALCOMM Incorporated , THOMSON, Steven S. , RYCHLIK, Bohuslav , IRANLI, Ali , SALSBERY, Brian J. , SUR, Sumit , GARGASH, Norman S.
发明人： THOMSON, Steven S. , RYCHLIK, Bohuslav , IRANLI, Ali , SALSBERY, Brian J. , SUR, Sumit , GARGASH, Norman S.
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method of dynamically controlling power within a central processing unit is disclosed and may include entering an idle state, reviewing a previous busy cycle immediately prior to the idle state, and based on the previous busy cycle determining a CPU frequency for a next busy cycle.
摘要翻译：公开了一种在中央处理单元内动态控制功率的方法，并且可以包括进入空闲状态，在空闲状态之前立即查看先前的忙碌状态，并且基于先前的忙碌周期确定下一繁忙周期的CPU频率。

9. 发明申请

WO2011084329A1 SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER IN A VIRTUALIZED SYSTEM 审中-公开
标题翻译：在虚拟化系统中控制中央处理单元功率的系统和方法
公开(公告)号：WO2011084329A1
公开(公告)日：2011-07-14
申请号：PCT/US2010/059538
申请日：2010-12-08
申请人： QUALCOMM Incorporated , RYCHLIK, Bohuslav , IRANLI, Ali , SALSBERY, Brian J. , SUR, Sumit , THOMSON, Steven S.
发明人： RYCHLIK, Bohuslav , IRANLI, Ali , SALSBERY, Brian J. , SUR, Sumit , THOMSON, Steven S.
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/5027 , G06F9/5094 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/22
摘要： A method of dynamically controlling power within a multicore central processing unit is disclosed and includes executing a plurality of virtual cores, virtually executing one or more tasks, one or more threads, or a combination thereof at the virtual cores, and physically executing one or more tasks, one or more threads, or a combination thereof at a zeroth physical core. The method may further include receiving a degree of parallelism in a workload of a plurality of virtual cores and determining whether the degree of parallelism in the workload of the virtual cores is equal to a first wake condition.
摘要翻译：公开了一种在多核中央处理单元内动态控制功率的方法，包括在虚拟核心处执行多个虚拟核，虚拟地执行一个或多个任务，一个或多个线程或其组合，以及物理地执行一个或多个任务，一个或多个线程，或其组合在第零个物理核心。该方法还可以包括在多个虚拟核心的工作负载中接收一定程度的并行性，并且确定虚拟核心的工作负载中的并行度是否等于第一唤醒条件。

10. 发明申请

WO2011022114A1 ATOMIC MEMORY DEVICE 审中-公开
标题翻译：原子记忆装置
公开(公告)号：WO2011022114A1
公开(公告)日：2011-02-24
申请号：PCT/US2010/039095
申请日：2010-06-17
申请人： RAMBUS INC. , SHEFFLER, Thomas , LAI, Lawrence , PENG, Liang , RYCHLIK, Bohuslav
发明人： SHEFFLER, Thomas , LAI, Lawrence , PENG, Liang , RYCHLIK, Bohuslav
IPC分类号： G11C8/04 , G11C7/10 , G11C7/22
CPC分类号： G06F12/023 , G06F2212/2024 , G11C7/1006 , G11C7/1039 , G11C7/22 , G11C8/10 , G11C2207/107
摘要： In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command.
摘要翻译：在具有存储器核心的集成电路存储器件中，响应于存储器访问命令，从存储器内核中的地址指定位置检索第一数据值。响应于存储器访问命令，从存储器件输出第一数据值，并且响应于存储器访问命令，将第二数据值存储在存储器内核中的地址指定位置中。

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