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1. 发明申请

WO2012103558A1 BUS CLOCK FREQUENCY SCALING FOR A BUS INTERCONNECT AND RELATED DEVICES, SYSTEMS, AND METHODS 审中-公开
标题翻译：总线互连的总线时钟频率和相关设备，系统和方法
公开(公告)号：WO2012103558A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/023194
申请日：2012-01-30
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard Gerard , GANASAN, Jaya Prakash Subramaniam , LEWIS, Brandon Wayne
发明人： HOFMANN, Richard Gerard , GANASAN, Jaya Prakash Subramaniam , LEWIS, Brandon Wayne
IPC分类号： G06F13/40 , G06F1/04 , G06F1/32
CPC分类号： G06F13/4022 , G06F1/06 , G06F1/3209 , G06F1/324 , Y02D10/126 , Y02D10/151
摘要： Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.
摘要翻译：公布了总线互连及相关设备，系统和方法的总线时钟频率缩放。在一个实施例中，总线互连包括可配置为将主端口连接到从端口的互连网络。总线互连时钟信号对互连网络进行时钟。控制器被配置为接收与通过主端口和从端口传送的业务相关的带宽信息。如果主端口和/或从端口的带宽满足相应的带宽条件，则控制器进一步被配置为扩展（例如，增加或减少）总线互连时钟信号的频率，以及 /或如果主端口的延迟满足主端口的相应等待时间条件。主端口和/或从端口也可以被重新配置以响应总线互连时钟信号的频率变化，以优化性能并节省功率。

2. 发明申请

WO2007106698A2 EFFICIENT EXECUTION OF MEMORY BARRIER BUS COMMANDS 审中-公开
标题翻译：内存障碍物总线命令的有效执行
公开(公告)号：WO2007106698A2
公开(公告)日：2007-09-20
申请号：PCT/US2007/063510
申请日：2007-03-07
申请人： QUALCOMM INCORPORATED , SULLIVAN, James Edward, Jr. , GANASAN, Jaya Prakash Subramaniam , HOFMANN, Richard Gerard
发明人： SULLIVAN, James Edward, Jr. , GANASAN, Jaya Prakash Subramaniam , HOFMANN, Richard Gerard
IPC分类号： G06F9/38
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译：本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。

3. 发明申请

WO2007048136A3 METHOD AND APPARATUS TO CLEAR SEMAPHORE RESERVATION 审中-公开
公开(公告)号：WO2007048136A3
公开(公告)日：2007-04-26
申请号：PCT/US2006/060136
申请日：2006-10-20
申请人： QUALCOMM INCORPORATED , SPEIER, Thomas Philip , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , GANASAN, Jaya Prakash Subramaniam
发明人： SPEIER, Thomas Philip , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , GANASAN, Jaya Prakash Subramaniam
IPC分类号： G06F9/46
摘要： Semaphore (116) operation manages exclusive access to a memory (114) that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is (102a), (102b) monitored by a memory controller. To clear an obsolete reservation status, a command signal is transmitted for a write operation to the memory while prohibiting update of the contents of a memory. The reservation status at the controller (104) is changed from a reservation state to a non-reservation state in response to receipt of the command signal.

4. 发明申请

WO2013040077A1 METHOD AND APPARATUS FOR ADAPTIVE HYSTERESIS TIMER ADJUSTMENTS FOR CLOCK GATING 审中-公开
标题翻译：用于时钟增益的自适应滞后定时器调整的方法和装置
公开(公告)号：WO2013040077A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/054922
申请日：2012-09-12
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard, Gerard , GANASAN, Jaya Prakash Subramaniam
发明人： HOFMANN, Richard, Gerard , GANASAN, Jaya Prakash Subramaniam
IPC分类号： G06F1/04
CPC分类号： G06F1/08 , G06F1/3237 , G06F1/3253 , Y02D10/128 , Y02D10/151
摘要： Apparatus and method for adaptive hysteresis timer adjustments for clock gating are disclosed. An apparatus comprises a transaction circuit configured to perform transactions. The apparatus further comprises a hysteresis timer having a hysteresis value and configured to start counting based on the hysteresis value when a transaction in the transaction circuit has been completed. The apparatus further comprises a hysteresis timer update circuit configured to monitor the hysteresis timer and the transaction circuit, store an adjustment state based on whether a new transaction is received before, coincident with or after the count of the hysteresis timer expires and adjust the hysteresis value based on the adjustment state.
摘要翻译：公开了用于时钟门控的自适应滞后定时器调整的装置和方法。一种装置包括被配置为执行交易的交易电路。该装置还包括具有迟滞值的滞后定时器，并且被配置为当交易电路中的交易已经完成时基于迟滞值开始计数。该装置还包括滞后定时器更新电路，其被配置为监视滞后定时器和事务电路，基于在迟滞计时器的计数到期之前是否接收到新的事务，并且调整滞后值来调整调整状态基于调整状态。

5. 发明申请

WO2012054754A1 ARBITRATING BUS TRANSACTIONS ON A COMMUNICATIONS BUS BASED ON BUS DEVICE HEALTH INFORMATION AND RELATED POWER MANAGEMENT 审中-公开
标题翻译：根据总线设备健康信息和相关电源管理对通信总线进行总线交易
公开(公告)号：WO2012054754A1
公开(公告)日：2012-04-26
申请号：PCT/US2011/057142
申请日：2011-10-20
申请人： QUALCOMM INCORPORATED , DUROIU, Cristian , GANASAN, Jaya Prakash Subramaniam , CHAMARTY, Vinod , SCHAFFER, Mark Michael , STUBBS, Joshua H. , GIBSON, Robert N. , TIRI, Kris , KHAN, Moinul H. , RYCHLIK, Bohuslav , GADELRAB, Serag , BOOTH, Simon
发明人： DUROIU, Cristian , GANASAN, Jaya Prakash Subramaniam , CHAMARTY, Vinod , SCHAFFER, Mark Michael , STUBBS, Joshua H. , GIBSON, Robert N. , TIRI, Kris , KHAN, Moinul H. , RYCHLIK, Bohuslav , GADELRAB, Serag , BOOTH, Simon
IPC分类号： G06F13/362
CPC分类号： G06F13/362 , Y02D10/14
摘要： Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.
摘要翻译：公开了用于基于健康信息在通信总线上仲裁总线事务的设备，系统，方法和计算机可读介质。主设备的健康信息可用于调整主设备总线事务的优先级，以满足主设备的服务质量要求。在一个实施例中，总线互连被提供和配置为将总线事务从多个主设备中的任一个传送到耦合总线互连的从设备。总线互连还被配置为将多个主设备中的每一个的健康信息映射到虚拟优先级空间中。总线互连还被配置为将虚拟优先级空间转换为多个主设备中的每一个的物理优先级。总线互连还被配置为基于多个主设备的物理优先级来仲裁多个主设备的总线事务。

6. 发明申请

WO2007024677A2 WEIGHTED BUS ARBITRATION BASED ON TRANSFER DIRECTION AND CONSUMED BANDWIDTH 审中-公开
标题翻译：基于传输方向和消费带宽的加权总线仲裁
公开(公告)号：WO2007024677A2
公开(公告)日：2007-03-01
申请号：PCT/US2006/032302
申请日：2006-08-18
申请人： QUALCOMM Incorporated , SCHAFFER, Mark, Michael , HOFMANN, Richard, Gerard , GANASAN, Jaya, Prakash, Subramaniam
发明人： SCHAFFER, Mark, Michael , HOFMANN, Richard, Gerard , GANASAN, Jaya, Prakash, Subramaniam
CPC分类号： G06F13/362
摘要： A bus arbitration algorithm precisely controls the relative bus channel bandwidth allocated to each master device by considering the direction of, and/or the bus channel bandwidth consumed by, a bus transaction. At least one weighting register is associated with each master device; in one embodiment, one weighting register per bus channel. The register is periodically loaded with a proportionate share of the available bus bandwidth. Upon being granted a bus transaction on a bus channel, the corresponding weighting register is decremented by an amount that reflects the bus channel bandwidth consumed by the transaction, measured in amount of data transferred or number of bus data transfer cycles required to complete the transaction. In the case of equal initial allocation of relative bandwidth share, master devices that consume bus channel bandwidth will have relatively low priority; master devices that do not consume bus channel bandwidth retain relatively high priority.
摘要翻译：总线仲裁算法通过考虑总线事务消耗的方向和/或总线信道带宽来精确地控制分配给每个主设备的相对总线信道带宽。至少一个加权寄存器与每个主设备相关联; 在一个实施例中，每个总线信道有一个加权寄存器。寄存器定期加载可用总线带宽的比例份额。在总线信道被授予总线事务后，对应的加权寄存器减少反映交易消耗的总线信道带宽的量，以传输的数据量或完成交易所需的总线数据传送周期的数量进行测量。在初始分配相对带宽份额相同的情况下，消耗总线信道带宽的主设备优先级相对较低; 不消耗总线信道带宽的主设备保持较高的优先级。

7. 发明申请

WO2006073927A1 METHOD AND APPARATUS OF REDUCING TRANSFER LATENCY IN AN SOC INTERCONNECT 审中-公开
标题翻译：在SOC互连中减少传输延迟的方法和装置
公开(公告)号：WO2006073927A1
公开(公告)日：2006-07-13
申请号：PCT/US2005/047038
申请日：2005-12-23
申请人： QUALCOMM INCORPORATED , GANASAN, Jaya, Prakash, Subramaniam , REMAKLUS, Perry, Willmann, Jr.
发明人： GANASAN, Jaya, Prakash, Subramaniam , REMAKLUS, Perry, Willmann, Jr.
IPC分类号： G06F13/364
CPC分类号： G06F13/364
摘要： Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.
摘要翻译：本发明的实施例涉及用于减少芯片上的系统中的传输等待时间的方法和装置，该芯片上的系统包括总线主机，总线从机和仲裁器，其中总线主机，总线从机和仲裁器处于电子通讯。请求从总线主机发送到仲裁器，其中优先级信号与等待时间要求相关联。仲裁器在将请求发送到总线从设备之前审查延迟要求，并确定是否提升优先级信号。然后，请求信号从仲裁器发送到总线从站。总线从站满足请求并发送对请求的响应，其中传输包括优先级信号。

8. 发明申请

WO2005071557A2 A MULTIPLE ADDRESS TWO CHANNEL BUS STRUCTURE 审中-公开
标题翻译：多地址双通道总线结构
公开(公告)号：WO2005071557A2
公开(公告)日：2005-08-04
申请号：PCT/US2005/001590
申请日：2005-01-20
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard Gerard , GANASAN, Jaya Prakash Subramaniam , LOWERY, Thomas John , REMAKLUS, Perry Willmann, Jr.
发明人： HOFMANN, Richard Gerard , GANASAN, Jaya Prakash Subramaniam , LOWERY, Thomas John , REMAKLUS, Perry Willmann, Jr.
IPC分类号： G06F13/42
CPC分类号： G06F13/423 , G06F13/4243
摘要： A processing system is disclosed with a sending component and a receiving component connected by a multiple address two channel bus. The sending device may broadcast on the first channel of the bus read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data. The sending component may also broadcast the read and write address information multiple address locations at a time. The receiving component may store the write data broadcast on the first channel based on the write address information, retrieve the read data from the receiving component based on the read address information, and broadcasting the retrieved read data on the second channel of the bus.
摘要翻译：公开了一种具有通过多地址双通道总线连接的发送组件和接收组件的处理系统。发送设备可以在总线的第一信道上广播包括多个读取地址位置的读取地址信息，包括多个写入地址位置的写入地址信息以及写入数据。发送组件也可以一次广播读取和写入地址信息多个地址位置。接收组件可以基于写地址信息存储在第一信道上广播的写数据，基于读地址信息从接收组件检索读数据，并且在总线的第二信道上广播检索到的读数据。 / p>

9. 发明申请

WO2012088464A1 METHOD AND APPARATUS FOR REDUCING DYNAMIC POWER WITHIN SYSTEM-ON-A-CHIP ROUTING RESOURCES 审中-公开
标题翻译：用于减少系统在线路由资源中的动态功率的方法和装置
公开(公告)号：WO2012088464A1
公开(公告)日：2012-06-28
申请号：PCT/US2011/066952
申请日：2011-12-22
申请人： QUALCOMM Incorporated , GANASAN, Jaya, Prakash, Subramaniam , SHIRLEN, Martyn, Ryan
发明人： GANASAN, Jaya, Prakash, Subramaniam , SHIRLEN, Martyn, Ryan
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： A method for saving power in transmission of data across buses. By knowing the power characteristics of a bus and characteristics of data to be transmitted across the bus, the data can be encoded in such a fashion as to conserve system power over transmitting the same data in an unencoded format across the bus. The encoding method may be selected before transmission of the data across the bus, and may change depending on the data to be transmitted across the bus.
摘要翻译：一种在总线上传输数据的方法。通过了解总线的功率特性和通过总线传输的数据的特性，可以以这样的方式对数据进行编码，以便通过跨总线以未编码格式发送相同数据节省系统功率。可以在通过总线传输数据之前选择编码方法，并且可以根据要通过总线传输的数据而改变。

10. 发明申请

WO2006102667A2 ENFORCING STRONGLY-ORDERED REQUESTS IN A WEAKLY-ORDERED PROCESSING SYSTEM 审中-公开
标题翻译：在弱势处理系统中执行强大的要求
公开(公告)号：WO2006102667A2
公开(公告)日：2006-09-28
申请号：PCT/US2006/011174
申请日：2006-03-23
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard, Gerard , SARTORIUS, Thomas, Andrew , SPEIER, Thomas, Philip , GANASAN, Jaya, Prakash, Subramaniam , DIEFFENDERFER, James, Norris , SULLIVAN, James, Edward
发明人： HOFMANN, Richard, Gerard , SARTORIUS, Thomas, Andrew , SPEIER, Thomas, Philip , GANASAN, Jaya, Prakash, Subramaniam , DIEFFENDERFER, James, Norris , SULLIVAN, James, Edward
IPC分类号： G06F13/16 , G06F9/38
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译：本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。处理系统包括多个存储器件和多个处理器。每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

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