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1. 发明申请

WO9524057A3 LOW VOLTAGE ONE TRANSISTOR FLASH EEPROM CELL USING FOWLER-NORDHEIM PROGRAMMING AND ERASE 审中-公开
标题翻译：使用FOWLER-NORDHEIM编程和擦除的低电压一个晶体管闪存EEPROM单元
公开(公告)号：WO9524057A3
公开(公告)日：1995-11-23
申请号：PCT/US9502240
申请日：1995-02-22
申请人： ROHM CORP
发明人： CHANG SHANG-DE , CHANG JIA-HWANG , CHOW EDWIN
IPC分类号： G11C16/04 , G11C16/02 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , G11C17/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/345 , G11C16/0416 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C16/3459 , H01L27/115 , H01L29/7883
摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.
摘要翻译：在能够使用Fowler-Nordheim隧道进行编程和擦除并且能够使用低电压操作的单晶体管电可擦除可编程存储器件中，源极和漏极区域（14,12）中的每一个的部分与第一栅极介电层（18），并且所述互互电介质层（26）被选择为具有高介电常数，以便使浮置栅极（24），控制栅极（28），源极（14）和漏极（12）之间的电容耦合比最大化）。通过首先将单元格块升高到高电压阈值并单独降低所选单元格的电压阈值来设置阵列中的单元的逻辑状态。

2. 发明专利

AT238610T 未知
公开(公告)号：AT238610T
公开(公告)日：2003-05-15
申请号：AT99200055
申请日：1995-02-22
申请人： ROHM CORP
发明人： CHANG SHANG-DE , CHANG JIA-HWANG , CHOW EDWIN
IPC分类号： G11C16/04 , G11C16/02 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , G11C17/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： In a single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages, portions of each of the source and drain regions (14, 12) overlap with the first gate dielectric layer (18), and the interpoly dielectric layer (26) is chosen to have a high dielectric constant so as to maximise the capacitive coupling ratio between floating gate (24), control gate (28), source (14), and drain (12). The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

3. 发明专利

DE69523743T2 未知
公开(公告)号：DE69523743T2
公开(公告)日：2002-08-01
申请号：DE69523743
申请日：1995-02-22
申请人： ROHM CORP
发明人： CHANG SHANG-DE , CHANG JIA-HWANG , CHOW EDWIN
IPC分类号： G11C16/04 , G11C16/02 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , G11C17/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： In a single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages, portions of each of the source and drain regions (14, 12) overlap with the first gate dielectric layer (18), and the interpoly dielectric layer (26) is chosen to have a high dielectric constant so as to maximise the capacitive coupling ratio between floating gate (24), control gate (28), source (14), and drain (12). The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

4. 发明专利

DE3587799T2 未知
公开(公告)号：DE3587799T2
公开(公告)日：1994-07-28
申请号：DE3587799
申请日：1985-11-05
申请人： ROHM CORP
发明人： MUKHERJEE SATYEN , CHANG THOMAS
IPC分类号： G11C17/00 , G11C14/00 , G11C16/04 , G11C16/10 , G11C16/16 , H01L21/28 , H01L21/321 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/08 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/62 , H01L29/60 , G11C16/02
摘要： A method of making a capacitive coupling device, especially in a transistor of an EEPROM, and such device. The interpoly dielectric layer (66) between control gate (68) and floating gate (64) consists of a thin layer of oxide and a layer of tantalum pentoxide so as to obtain a high capacitance value with a small physical size. This allows EEPROM cells which require substantially lower programming and erasing voltages.

5. 发明专利

DE3884037D1 未知
公开(公告)号：DE3884037D1
公开(公告)日：1993-10-21
申请号：DE3884037
申请日：1988-04-13
申请人： ROHM CORP
发明人： GOETTING ERICH
IPC分类号： G06F7/00 , H03K17/22 , H03K19/177
摘要： An improved architecture for programming an output cell (macro cell) in a PLD. The memory cells for the macro cell (18) are stored in the main array (10) itself. Upon power-up, a power-on sense circuit (40) senses the presence of power and enables an architecture portion (14) of the main array (10) while disabling the rest (12) of the main array (10). The power-on sense signal (POS) also enables a path from the output of the array to the macro cell elements (18) to be programmed. When the power-on sense signal (POS) is removed a short time after power-up, this path is blocked so that the array outputs continue on their normal path and the architecture portion (14) of the array (10) is disabled while the rest (12) of the array (10) is enabled for normal operation.

6. 发明专利

DE3873392T2 未知
公开(公告)号：DE3873392T2
公开(公告)日：1993-04-08
申请号：DE3873392
申请日：1988-04-13
申请人： ROHM CORP
发明人： GOETTING ERICH
IPC分类号： H01H85/46 , G06F7/00 , G06F12/14 , G06F21/02 , G06F21/24 , G11C7/24 , G11C16/22 , H01H37/76 , H01L21/82 , H01L27/10 , H03K19/177
摘要： One of the programmable elements of the array (20) is designated as a security element (22), and its output is coupled to a latching mechanism (30). The output of the latching mechanism (30) is coupled to a mechanism (36) for disabling the read output of the array (20). The latching mechanism (30) is enabled for a short time by a pulse when power is applied to the circuit. Thus, when power is first applied, the security fuse (22) has not been set and the latch output will allow data to be read. While power is applied, all of the programmable elements can be set, including the security element (22). All the elements, including the security fuse (22), can then be verified by reading them out. When power is turned off and subsequently reapplied, the latch (30) will then be enabled and the set security fuse level will appear at the latch output, thereby disabling the reading out of the program data. The present invention thus allows verification of the setting of the security fuse (22) and verification of the other programmable elements after the security fuse (22) has been set.

7. 发明专利

AT104473T 未知
公开(公告)号：AT104473T
公开(公告)日：1994-04-15
申请号：AT85114090
申请日：1985-11-05
申请人： ROHM CORP
发明人： MUKHERJEE SATYEN , CHANG THOMAS
IPC分类号： G11C17/00 , G11C14/00 , G11C16/04 , G11C16/10 , G11C16/16 , H01L21/28 , H01L21/321 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/08 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/62 , H01L29/60 , G11C16/02
摘要： A method of making a capacitive coupling device, especially in a transistor of an EEPROM, and such device. The interpoly dielectric layer (66) between control gate (68) and floating gate (64) consists of a thin layer of oxide and a layer of tantalum pentoxide so as to obtain a high capacitance value with a small physical size. This allows EEPROM cells which require substantially lower programming and erasing voltages.

8. 发明专利

AT94705T 未知
公开(公告)号：AT94705T
公开(公告)日：1993-10-15
申请号：AT88303292
申请日：1988-04-13
申请人： ROHM CORP
发明人： GOETTING ERICH
IPC分类号： G06F7/00 , H03K17/22 , H03K19/177
摘要： An improved architecture for programming an output cell (macro cell) in a PLD. The memory cells for the macro cell (18) are stored in the main array (10) itself. Upon power-up, a power-on sense circuit (40) senses the presence of power and enables an architecture portion (14) of the main array (10) while disabling the rest (12) of the main array (10). The power-on sense signal (POS) also enables a path from the output of the array to the macro cell elements (18) to be programmed. When the power-on sense signal (POS) is removed a short time after power-up, this path is blocked so that the array outputs continue on their normal path and the architecture portion (14) of the array (10) is disabled while the rest (12) of the array (10) is enabled for normal operation.

9. 发明专利

AT79205T 未知
公开(公告)号：AT79205T
公开(公告)日：1992-08-15
申请号：AT88303293
申请日：1988-04-13
申请人： ROHM CORP
发明人： GOETTING ERICH
IPC分类号： H01H85/46 , G06F7/00 , G06F12/14 , G06F21/02 , G06F21/24 , G11C7/24 , G11C16/22 , H01H37/76 , H01L21/82 , H01L27/10 , H03K19/177
摘要： One of the programmable elements of the array (20) is designated as a security element (22), and its output is coupled to a latching mechanism (30). The output of the latching mechanism (30) is coupled to a mechanism (36) for disabling the read output of the array (20). The latching mechanism (30) is enabled for a short time by a pulse when power is applied to the circuit. Thus, when power is first applied, the security fuse (22) has not been set and the latch output will allow data to be read. While power is applied, all of the programmable elements can be set, including the security element (22). All the elements, including the security fuse (22), can then be verified by reading them out. When power is turned off and subsequently reapplied, the latch (30) will then be enabled and the set security fuse level will appear at the latch output, thereby disabling the reading out of the program data. The present invention thus allows verification of the setting of the security fuse (22) and verification of the other programmable elements after the security fuse (22) has been set.

10. 发明专利

DE3588238T2 未知
公开(公告)号：DE3588238T2
公开(公告)日：2003-02-06
申请号：DE3588238
申请日：1985-11-05
申请人： ROHM CORP
发明人： MUKHERJEE SATYEN , CHANG THOMAS
IPC分类号： G11C17/00 , G11C14/00 , G11C16/04 , G11C16/10 , G11C16/16 , H01L21/28 , H01L21/321 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/08 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792
摘要： A method of making a capacitive coupling device, especially in a transistor of an EEPROM, and such device. The interpoly dielectric layer (66) between control gate (68) and floating gate (64) consists of a thin layer of oxide and a layer of tantalum pentoxide so as to obtain a high capacitance value with a small physical size. This allows EEPROM cells which require substantially lower programming and erasing voltages.

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