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1. 发明申请

WO2011077453A2 FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS 审中-公开
标题翻译：用于处理基于雷达的信号的FPGA系统
公开(公告)号：WO2011077453A2
公开(公告)日：2011-06-30
申请号：PCT/IN2010/000833
申请日：2010-12-21
申请人： THE TATA POWER COMPANY LTD. , DIKSHIT, Raghukul Bhushan , REDDY, Pradeep N.
发明人： DIKSHIT, Raghukul Bhushan , REDDY, Pradeep N.
IPC分类号： G06F17/10
CPC分类号： G01S7/064 , G01S7/295
摘要： A Field Programmable Gate Array (FPGA) system is provided to read input radar signals and produce an output for plotting a regular radar display on a pre-defined map to obtain an accurate and easy-to-read rendition of the position of a target being mapped by the radar. Analog radar signals received are converted to digital signals by an RSC. CFAR mechanism is used to condition the digital signals which are then compressed to create video frames by a B-Scope. The created video frames are stored in a DDR storage means via a DDR arbiter having a pre-determined number of read/write ports, each port having a pre-defined priority. The created video frames are blended with a synthetic video to produce a fused video by alpha blending technique. An alpha display provides non-interlaced scanning for raster display of the fused video at a pre-determined resolution.
摘要翻译：提供现场可编程门阵列（FPGA）系统来读取输入雷达信号并产生用于在预定义的地图上绘制规则雷达显示的输出，以获得准确和易于阅读再现由雷达映射的目标的位置。接收到的模拟雷达信号由RSC转换为数字信号。 CFAR机制用于调节数字信号，然后通过B-Scope对数字信号进行压缩以创建视频帧。通过具有预定数量的读/写端口的DDR仲裁器将创建的视频帧存储在DDR存储装置中，每个端口具有预定义的优先级。创建的视频帧与合成视频混合，通过alpha混合技术生成融合视频。字幕显示以预先确定的分辨率为融合视频的光栅显示提供非隔行扫描。

2. 发明申请

WO2022232442A2 MULTIPLEX CRISPR/CAS9-MEDIATED TARGET GENE ACTIVATION SYSTEM 审中-公开
公开(公告)号：WO2022232442A2
公开(公告)日：2022-11-03
申请号：PCT/US2022/026805
申请日：2022-04-28
申请人： SALK INSTITUTE FOR BIOLOGICAL STUDIES , IZPISUA BELMONTE, Juan Carlos , WANG, Chao , LIAO, Hsin-Kai , REDDY, Pradeep
发明人： IZPISUA BELMONTE, Juan Carlos , WANG, Chao , LIAO, Hsin-Kai , REDDY, Pradeep
IPC分类号： C12N1/20 , C12N15/87 , C12N9/12 , C12N15/113 , C12N2310/16 , C12N2310/20 , C12N2310/3519 , C12N2320/31 , C12N2330/51 , C12N2750/14143
摘要： Provided herein are multiplex crRNAs and multiplex sgRNAs, as well as RNA molecules thereof. Also provided are compositions and kits including the multiplex crRNAs and sgRNAs, which can be used in a multiplex targeted gene activation (mTGA) system. Also provided are methods that include administering a therapeutically effective amount of the mTGA system to a subject. In some examples, the method treats a disease associated with reduced or no expression of a gene, such as type I diabetes, Duchenne muscular dystrophy, a liver disease, or acute kidney disease.

3. 发明申请

WO2012131701A2 FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS FOR AERIAL VIEW DISPLAY 审中-公开
标题翻译：用于处理基于雷达的信号用于空中视频显示的FPGA系统
公开(公告)号：WO2012131701A2
公开(公告)日：2012-10-04
申请号：PCT/IN2012/000161
申请日：2012-03-07
申请人： THE TATA POWER COMPANY LTD. , DIKSHIT, Raghukul , REDDY, Pradeep
发明人： DIKSHIT, Raghukul , REDDY, Pradeep
IPC分类号： G06F17/10
CPC分类号： G01S7/298 , G01S7/032 , G01S7/12
摘要： A Field Programmable Gate Array (FPGA) system to read input radar signals and produce an output for plotting an aerial radar display on a pre-defined map to obtain a rendition of the position of a target being mapped. Analog radar signals received are converted to digital signals by an RSC. Received digital signal and radar control signal are used by PPI to create aerial scan video frames. The created frames are stored in a DDR2 SDRAM storage means via a DDR2 multiport controller having a pre-determined number of read/write ports, each port having a pre-defined priority. The created frames are positioned and resized in raster zoom-pan controller means and then blended with synthetic video generated by a host processor to produce a fused video by alpha blender using alpha blending technique. An alpha blender provides non-interlaced scanning for raster display of the fused video at a pre¬ determined resolution.
摘要翻译：现场可编程门阵列（FPGA）系统，用于读取输入的雷达信号并产生输出，用于在预定义的地图上绘制空中雷达显示，以获得被映射的目标的位置的再现。接收的模拟雷达信号通过RSC转换成数字信号。接收的数字信号和雷达控制信号被PPI用于创建航空扫描视频帧。创建的帧通过具有预定数量的读/写端口的DDR2多端口控制器存储在DDR2 SDRAM存储装置中，每个端口具有预定义的优先级。创建的框架以光栅缩放平移控制器的方式定位和调整大小，然后与由主机处理器生成的合成视频相混合，通过Alpha混合技术通过alpha混合器产生融合视频。 Alpha混合器以预定的分辨率为融合视频的光栅显示提供非隔行扫描。

4. 发明申请

WO2011077453A3 FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS 审中-公开
标题翻译：用于处理基于雷达信号的FPGA系统
公开(公告)号：WO2011077453A3
公开(公告)日：2011-10-06
申请号：PCT/IN2010000833
申请日：2010-12-21
申请人： TATA POWER COMPANY LTD , DIKSHIT RAGHUKUL BHUSHAN , REDDY PRADEEP N
发明人： DIKSHIT RAGHUKUL BHUSHAN , REDDY PRADEEP N
IPC分类号： G06F17/10
CPC分类号： G01S7/064 , G01S7/295
摘要： A Field Programmable Gate Array (FPGA) system is provided to read input radar signals and produce an output for plotting a regular radar display on a pre-defined map to obtain an accurate and easy-to-read rendition of the position of a target being mapped by the radar. Analog radar signals received are converted to digital signals by an RSC. CFAR mechanism is used to condition the digital signals which are then compressed to create video frames by a B-Scope. The created video frames are stored in a DDR storage means via a DDR arbiter having a pre-determined number of read/write ports, each port having a pre-defined priority. The created video frames are blended with a synthetic video to produce a fused video by alpha blending technique. An alpha display provides non-interlaced scanning for raster display of the fused video at a pre-determined resolution.
摘要翻译：提供现场可编程门阵列（FPGA）系统来读取输入的雷达信号并产生一个输出，用于在预定义的地图上绘制常规的雷达显示，以获得准确和易于阅读的目标位置的演示由雷达映射接收的模拟雷达信号通过RSC转换为数字信号。 CFAR机制用于调节数字信号，然后通过B-Scope压缩数字信号以创建视频帧。所创建的视频帧通过具有预定数量的读/写端口的DDR仲裁器存储在DDR存储装置中，每个端口具有预定义的优先级。所创建的视频帧与合成视频混合，通过alpha混合技术产生融合视频。阿尔法显示器以预定分辨率提供非隔行扫描以对融合视频进行光栅显示。

5. 发明申请

WO2012131701A3 FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS FOR AERIAL VIEW DISPLAY 审中-公开
标题翻译：用于处理基于雷达的信号用于空中视频显示的FPGA系统
公开(公告)号：WO2012131701A3
公开(公告)日：2012-12-27
申请号：PCT/IN2012000161
申请日：2012-03-07
申请人： TATA POWER COMPANY LTD , DIKSHIT RAGHUKUL , REDDY PRADEEP
发明人： DIKSHIT RAGHUKUL , REDDY PRADEEP
IPC分类号： G06F17/10
CPC分类号： G01S7/298 , G01S7/032 , G01S7/12
摘要： A Field Programmable Gate Array (FPGA) system to read input radar signals and produce an output for plotting an aerial radar display on a pre-defined map to obtain a rendition of the position of a target being mapped. Analog radar signals received are converted to digital signals by an RSC. Received digital signal and radar control signal are used by PPI to create aerial scan video frames. The created frames are stored in a DDR2 SDRAM storage means via a DDR2 multiport controller having a pre-determined number of read/write ports, each port having a pre-defined priority. The created frames are positioned and resized in raster zoom-pan controller means and then blended with synthetic video generated by a host processor to produce a fused video by alpha blender using alpha blending technique. An alpha blender provides non-interlaced scanning for raster display of the fused video at a pre-determined resolution.
摘要翻译：现场可编程门阵列（FPGA）系统，用于读取输入的雷达信号，并产生一个输出，用于在预定义的地图上绘制空中雷达显示，以获得被映射目标的位置的再现。接收的模拟雷达信号通过RSC转换为数字信号。接收的数字信号和雷达控制信号被PPI用于创建航空扫描视频帧。创建的帧通过具有预定数量的读/写端口的DDR2多端口控制器存储在DDR2 SDRAM存储装置中，每个端口具有预定义的优先级。所创建的框架以光栅缩放平移控制器方式定位和调整大小，然后与由主机处理器生成的合成视频相混合，通过Alpha混合技术通过alpha混合器产生融合视频。 Alpha混合器提供非隔行扫描，以预定分辨率光栅显示融合视频。

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