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1. 发明申请

WO2011077453A2 FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS 审中-公开
标题翻译：用于处理基于雷达的信号的FPGA系统
公开(公告)号：WO2011077453A2
公开(公告)日：2011-06-30
申请号：PCT/IN2010/000833
申请日：2010-12-21
申请人： THE TATA POWER COMPANY LTD. , DIKSHIT, Raghukul Bhushan , REDDY, Pradeep N.
发明人： DIKSHIT, Raghukul Bhushan , REDDY, Pradeep N.
IPC分类号： G06F17/10
CPC分类号： G01S7/064 , G01S7/295
摘要： A Field Programmable Gate Array (FPGA) system is provided to read input radar signals and produce an output for plotting a regular radar display on a pre-defined map to obtain an accurate and easy-to-read rendition of the position of a target being mapped by the radar. Analog radar signals received are converted to digital signals by an RSC. CFAR mechanism is used to condition the digital signals which are then compressed to create video frames by a B-Scope. The created video frames are stored in a DDR storage means via a DDR arbiter having a pre-determined number of read/write ports, each port having a pre-defined priority. The created video frames are blended with a synthetic video to produce a fused video by alpha blending technique. An alpha display provides non-interlaced scanning for raster display of the fused video at a pre-determined resolution.
摘要翻译：提供现场可编程门阵列（FPGA）系统来读取输入雷达信号并产生用于在预定义的地图上绘制规则雷达显示的输出，以获得准确和易于阅读再现由雷达映射的目标的位置。接收到的模拟雷达信号由RSC转换为数字信号。 CFAR机制用于调节数字信号，然后通过B-Scope对数字信号进行压缩以创建视频帧。通过具有预定数量的读/写端口的DDR仲裁器将创建的视频帧存储在DDR存储装置中，每个端口具有预定义的优先级。创建的视频帧与合成视频混合，通过alpha混合技术生成融合视频。字幕显示以预先确定的分辨率为融合视频的光栅显示提供非隔行扫描。

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