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1. 发明授权

US6010954A Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices 失效
标题翻译： Cmos门结构，用于将0.1％以上设备的自杀过程整合
公开(公告)号：US6010954A
公开(公告)日：2000-01-04
申请号：US156359
申请日：1998-09-18
申请人： Chaw Sing Ho , R. P. G. Karunasiri , Soo Jin Chua , Kin Leong Pey , Kong Hean Lee
发明人： Chaw Sing Ho , R. P. G. Karunasiri , Soo Jin Chua , Kin Leong Pey , Kong Hean Lee
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L21/18 , H01L21/283 , H01L21/335 , H01L21/461
CPC分类号： H01L29/665 , H01L21/28114 , H01L29/42376 , H01L29/66545
摘要： A method to form a "mushroom shaped" gate structure 18 22 44A 70 that increases the top gate silicide contact area and improves the salicide process, especially TiSi.sub.2 salicide. The novel upper gate extensions 44A increase the top gate surface area so that the silicide gate contacts 70 will have a low resistivity. The invention includes forming a gate stack 18 22 26 comprised of a gate oxide layer 18, a center gate portion 22 and a hard mask 26. Next, we form a first insulating layer 40 over the gate stack 22 26 18. The hard mask 26 and a first thickness of the first insulating layer 40 are removed to expose sidewalls of the center gate portion 22. A second conductive layer 44 is formed over the first insulating layer 46 and the center gate portion 22. The second conductive layer 44 is etched to form critical rounded upper gate extensions 44A on the sidewalls of the center gate portion 22. Lower rectangular sidewall spacers 52 are formed on the sidewalls of the center gate portion 22. Source/drain regions 54 are formed. A salicide process forms silicide source/drain contacts 64 and forms extra large silicided gate contacts 70 to reduce parasitic resistance.
摘要翻译：形成增加顶栅硅化物接触面积并改善自对准硅化物工艺的“蘑菇形”门结构18 22 44A 70的方法，特别是TiSi 2自对准硅化物。新颖的上部栅极延伸部分44A增加了顶部栅极表面积，使得硅化物栅极接触70将具有低电阻率。本发明包括形成由栅极氧化物层18，中心栅极部分22和硬掩模26组成的栅极堆叠18 22 26.接下来，我们在栅极叠层22 26上形成第一绝缘层40.硬掩模26 并且去除第一绝缘层40的第一厚度以暴露中心栅极部分22的侧壁。第二导电层44形成在第一绝缘层46和中心栅极部分22上。第二导电层44被蚀刻到在中心栅极部分22的侧壁上形成关键的圆形上部栅极延伸部分44A。下部矩形侧壁间隔件52形成在中心栅极部分22的侧壁上。形成源极/漏极区域54。自对准硅化物工艺形成硅化物源极/漏极触点64并形成特大的硅化物栅极触点70以减小寄生电阻。

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