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1. 发明授权

US07143500B2 Method to prevent damage to probe card 失效
标题翻译：防止探针卡损坏的方法
公开(公告)号：US07143500B2
公开(公告)日：2006-12-05
申请号：US09888689
申请日：2001-06-25
申请人： Phillip E. Byrd
发明人： Phillip E. Byrd
IPC分类号： H01H1/58
CPC分类号： G01R1/06766 , G01R1/07371 , G01R3/00 , G01R31/2886 , H05K1/0293 , H05K1/09 , H05K1/167 , H05K2201/068 , H05K2201/10053 , H05K2201/10181 , Y10T29/49004 , Y10T29/49005 , Y10T29/49107 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49139 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204
摘要： Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective fuses are provided in electrical communication with conductive traces and probe elements (e.g., probe needles) of a probe card. The fuses may be active or passive fuses, and are preferably self-resetting, repairable, and/or replaceable. Typically, the fuses will be interposed in, or located adjacent to, conductive traces residing over a surface of the probe card. Methods of fabricating a probe card are provided, as well as various probe card configurations. A semiconductor die testing system using the probe card is also provided.
摘要翻译：探头卡配置有适用于半导体裸片电气测试的保护电路，而不会损坏探针卡。提供保护性熔丝与探针卡的导电迹线和探针元件（例如探针）电连通。保险丝可以是有源或被动保险丝，并且优选地是自复位，可修复和/或可更换的。通常，保险丝将被置于位于探针卡的表面上方的导电迹线中或邻近其上。提供制造探针卡的方法以及各种探针卡配置。还提供了使用探针卡的半导体管芯测试系统。

2. 发明授权

US06819161B2 Structure for temporarily isolating a die from a common conductor to facilitate wafer level testing 失效
公开(公告)号：US06819161B2
公开(公告)日：2004-11-16
申请号：US10268901
申请日：2002-10-11
申请人： Phillip E. Byrd , Paul R. Sharratt
发明人： Phillip E. Byrd , Paul R. Sharratt
IPC分类号： G01F110
CPC分类号： G01R31/2856 , H01L22/32
摘要： The invention provides an apparatus for temporarily isolating a die from other dice on a wafer commonly connected to one or more common conductors. The conductors are connected to each die through a temporary isolation device, such as a diode. The common conductor supplies a signal to all dice during one set of test procedures, while the temporary isolation device can be used to isolate a die from the common conductor during another set of test procedures.

3. 发明授权

US07116124B2 Apparatus to prevent damage to probe card 失效
标题翻译：防止探针卡损坏的装置
公开(公告)号：US07116124B2
公开(公告)日：2006-10-03
申请号：US10327246
申请日：2002-12-20
申请人： Phillip E. Byrd
发明人： Phillip E. Byrd
IPC分类号： G01R31/02
CPC分类号： G01R1/06766 , G01R1/07371 , G01R3/00 , G01R31/2886 , H05K1/0293 , H05K1/09 , H05K1/167 , H05K2201/068 , H05K2201/10053 , H05K2201/10181 , Y10T29/49004 , Y10T29/49005 , Y10T29/49107 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49139 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204
摘要： Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective fuses are provided in electrical communication with conductive traces and probe elements (e.g., probe needles) of a probe card. The fuses may be active or passive fuses and are preferably self-resetting, repairable, and/or replaceable. Typically, the fuses will be interposed in, or located adjacent to, conductive traces residing over a surface of the probe card. Methods of fabricating a probe card are provided, as well as various probe card configurations. A semiconductor die testing system using the probe card is also provided.
摘要翻译：探头卡配置有适用于半导体裸片电气测试的保护电路，而不会损坏探针卡。提供保护性熔丝与探针卡的导电迹线和探针元件（例如探针）电连通。保险丝可以是有源或被动保险丝，并且优选地是自复位，可修复和/或可更换的。通常，保险丝将被置于位于探针卡的表面上方的导电迹线中或邻近其上。提供制造探针卡的方法以及各种探针卡配置。还提供了使用探针卡的半导体管芯测试系统。

4. 发明授权

US06809378B2 Structure for temporarily isolating a die from a common conductor to facilitate wafer level testing 失效
标题翻译：用于将管芯与公共导体暂时隔离以便于晶圆级测试的结构
公开(公告)号：US06809378B2
公开(公告)日：2004-10-26
申请号：US09941761
申请日：2001-08-30
申请人： Phillip E. Byrd , Paul R. Sharratt
发明人： Phillip E. Byrd , Paul R. Sharratt
IPC分类号： H07L31392
CPC分类号： G01R31/2856 , H01L22/32
摘要： The invention provides an apparatus for temporarily isolating a die from other dice on a wafer commonly connected to one or more common conductors. The conductors are connected to each die through a temporary isolation device, such as a diode. The common conductor supplies a signal to all dice during one set of test procedures, while the temporary isolation device can be used to isolate a die from the common conductor during another set of test procedures.
摘要翻译：本发明提供一种用于在与一个或多个公共导体共同连接的晶片上临时隔离晶粒与其它晶粒的装置。导体通过诸如二极管的临时隔离装置连接到每个管芯。在一组测试过程中，公共导体向所有骰子提供信号，而在另一组测试程序期间，可以使用临时隔离装置将模具与公共导体隔离。

5. 发明授权

US06762608B2 Apparatus and method for testing fuses 失效
标题翻译：用于测试保险丝的装置和方法
公开(公告)号：US06762608B2
公开(公告)日：2004-07-13
申请号：US10179543
申请日：2002-06-25
申请人： Tim Damon , Phillip E. Byrd
发明人： Tim Damon , Phillip E. Byrd
IPC分类号： H01H8530
CPC分类号： H01L22/34 , G01R31/07 , G01R31/316 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A voltage is applied across a control resistor, and the voltage is caused to decay. The decay is monitored by a testing circuit such as a comparator. When the voltage across the control resistor has decayed to a value less than or equal to a reference voltage in the comparator, a switch time period is established. Fuses in a memory device are tested against the established switch time period. The fuses are tested in a similar fashion: a voltage is applied across the fuse being tested, and the voltage is caused to decay. The comparator monitors the decay of the voltage across the fuse. If the resistance value of a fuse being tested is within specification, the comparator changes its state at a time equal to or less than the switch time period established for the control resistor. Testing time for fuses can further be minimized by having an external access to the reference in the comparator. In establishing the switch time period by applying a voltage across the control resistor, the voltage of the reference in the comparator is adjusted to establish quicker switch time periods against which fuses are tested. In this manner, testing time is minimized.
摘要翻译：一个电压施加在控制电阻上，电压会衰减。衰减由诸如比较器之类的测试电路来监测。当控制电阻两端的电压衰减到比较器中的参考电压小于或等于的值时，建立开关时间段。在建立的开关时间段内对存储器件中的保险丝进行测试。保险丝以类似的方式进行测试：在被测试的保险丝上施加电压，并且电压被衰减。比较器监视保险丝两端的电压的衰减。如果正在测试的保险丝的电阻值在指定范围内，则比较器将其状态改变为等于或小于为控制电阻建立的开关时间周期。通过外部访问比较器中的参考，可以进一步降低保险丝的测试时间。在通过在控制电阻器两端施加电压来建立开关时间周期时，调节比较器中参考电压，以确定测试熔断器的更快的开关时间周期。以这种方式，测试时间最小化。

6. 发明授权

US06410352B2 Apparatus and method for testing fuses 失效
公开(公告)号：US06410352B2
公开(公告)日：2002-06-25
申请号：US09854541
申请日：2001-05-14
申请人： Tim Damon , Phillip E. Byrd
发明人： Tim Damon , Phillip E. Byrd
IPC分类号： H01L2166
CPC分类号： H01L22/34 , G01R31/07 , G01R31/316 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A voltage is applied across a control resistor, and the voltage is caused to decay. The decay is monitored by a testing circuit such as a comparator. When the voltage across the control resistor has decayed to a value less than or equal to a reference voltage in the comparator, a switch time period is established. Fuses in a memory device are tested against the established switch time period. The fuses are tested in a similar fashion: a voltage is applied across the fuse being tested, and the voltage is caused to decay. The comparator monitors the decay of the voltage across the fuse. If the resistance value of a fuse being tested is within specification, the comparator changes its state at a time equal to or less than the switch time period established for the control resistor. Testing time for fuses can further be minimized by having an external access to the reference in the comparator. In establishing the switch time period by applying a voltage across the control resistor, the voltage of the reference in the comparator is adjusted to establish quicker switch time periods against which fuses are tested. In this manner, testing time is minimized.

7. 发明授权

US07219418B2 Method to prevent damage to probe card 有权
标题翻译：防止探针卡损坏的方法
公开(公告)号：US07219418B2
公开(公告)日：2007-05-22
申请号：US11138920
申请日：2005-05-26
申请人： Phillip E. Byrd
发明人： Phillip E. Byrd
IPC分类号： H01H69/02
CPC分类号： G01R1/06766 , G01R1/07371 , G01R3/00 , G01R31/2886 , H05K1/0293 , H05K1/09 , H05K1/167 , H05K2201/068 , H05K2201/10053 , H05K2201/10181 , Y10T29/49004 , Y10T29/49005 , Y10T29/49107 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49139 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204
摘要： Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective fuses are provided in electrical communication with conductive traces and probe elements (e.g., probe needles) of a probe card. The fuses may be active or passive fuses and are preferably self-resetting, repairable, and/or replaceable. Typically, the fuses will be interposed in, or located adjacent to, conductive traces residing over a surface of the probe card. Methods of fabricating a probe card are provided, as well as various probe card configurations. A semiconductor die testing system using the probe card is also provided.
摘要翻译：探头卡配置有适用于半导体裸片电气测试的保护电路，而不会损坏探针卡。提供保护性熔丝与探针卡的导电迹线和探针元件（例如探针）电连通。保险丝可以是有源或被动保险丝，并且优选地是自复位，可修复和/或可更换的。通常，保险丝将被置于位于探针卡的表面上方的导电迹线中或邻近其上。提供制造探针卡的方法以及各种探针卡配置。还提供了使用探针卡的半导体管芯测试系统。

8. 发明授权

US06981199B2 Method for arranging data output by semiconductor testers to packet-based devices under test 失效
标题翻译：将半导体测试仪输出的数据排列到基于分组的被测设备的方法
公开(公告)号：US06981199B2
公开(公告)日：2005-12-27
申请号：US10459336
申请日：2003-06-11
申请人： Phillip E. Byrd
发明人： Phillip E. Byrd
IPC分类号： G01R31/319 , G11C29/56 , H03M13/00
CPC分类号： G01R31/31926 , G01R31/31921 , G11C29/56
摘要： Method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator on a per-pin basis. Furthermore, the test method potentially reduces the number of packet words that has a combination of data generated from an APG and vector memory. Packet-based semiconductor devices are also disclosed.
摘要翻译：通过使用简化的测试数据包来测试基于分组的半导体器件的方法。简化的测试数据包是由传统的内存测试人员以一种格式生成的。在测试存储器件之前，简化的测试数据分组通过位于集成电路芯片，测试接口或测试仪上的测试模式电路重新对准另一种不同格式。测试方法潜在地减少必须使用每个引脚的算法模式生成器生成的数据块数。此外，测试方法潜在地减少了具有从APG和向量存储器生成的数据的组合的分组字的数量。还公开了基于分组的半导体器件。

9. 发明授权

US06760871B2 Circuit, system and method for arranging data output by semiconductor testers to packet-based devices under test 失效
标题翻译：用于将半导体测试仪输出的数据输出到基于分组的被测器件的电路，系统和方法
公开(公告)号：US06760871B2
公开(公告)日：2004-07-06
申请号：US09921767
申请日：2001-08-03
申请人： Phillip E. Byrd
发明人： Phillip E. Byrd
IPC分类号： G11C2900
CPC分类号： G01R31/31926 , G01R31/31921 , G11C29/56
摘要： An apparatus, system, and method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator on a per-pin basis. Furthermore, the test method potentially reduces the number of packet words that has a combination of data generated from an APG and vector memory. Packet-based semiconductor devices are also disclosed.
摘要翻译：一种通过使用简化的测试数据包来测试基于分组的半导体器件的装置，系统和方法。简化的测试数据包是由传统的内存测试人员以一种格式生成的。在测试存储器件之前，简化的测试数据分组通过位于集成电路芯片，测试接口或测试仪上的测试模式电路重新对准另一种不同格式。测试方法潜在地减少必须使用每个引脚的算法模式生成器生成的数据块数。此外，测试方法潜在地减少了具有从APG和向量存储器生成的数据的组合的分组字的数量。还公开了基于分组的半导体器件。

10. 发明授权

US06424161B1 Apparatus and method for testing fuses 失效
公开(公告)号：US06424161B1
公开(公告)日：2002-07-23
申请号：US09146688
申请日：1998-09-03
申请人： Tim Damon , Phillip E. Byrd
发明人： Tim Damon , Phillip E. Byrd
IPC分类号： G01R3102
摘要： A voltage is applied across a control resistor, and the voltage is caused to decay. The decay is monitored by a testing circuit such as a comparator. When the voltage across the control resistor has decayed to a value less than or equal to a reference voltage in the comparator, a switch time period is established. Fuses in a memory device are tested against the established switch time period. The fuses are tested in a similar fashion: a voltage is applied across the fuse being tested, and the voltage is caused to decay. The comparator monitors the decay of the voltage across the fuse. If the resistance value of a fuse being tested is within specification, the comparator changes its state at a time equal to or less than the switch time period established for the control resistor. Testing time for fuses can further be minimized by having an external access to the reference in the comparator. In establishing the switch time period by applying a voltage across the control resistor, the voltage of the reference in the comparator is adjusted to establish quicker switch time periods against which fuses are tested. In this manner, testing time is minimized.

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