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1. 发明申请

US20110073924A1 Non-Volatile Memory Cell and Layout Structure of Non-Volatile Memory Device 有权
标题翻译：非易失性存储器单元和非易失性存储器件的布局结构
公开(公告)号：US20110073924A1
公开(公告)日：2011-03-31
申请号：US12568953
申请日：2009-09-29
申请人： Hung-Lin SHIH , Bin Chen, JR. , Pei-Ching Yin , Hui-Fang Tsai
发明人： Hung-Lin SHIH , Bin Chen, JR. , Pei-Ching Yin , Hui-Fang Tsai
IPC分类号： H01L29/94
CPC分类号： H01L27/0207 , H01L27/11519 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory cell includes a semiconductor substrate with isolation structures formed therein and thereby transistor region and capacitor region are defined therein. A conductor is disposed over the isolation structures, the transistor region and a first-type doped well disposed in the capacitor region. The conductor includes a capacitor portion disposed over the first-type doped well, a transistor portion disposed over the transistor region, a first edge disposed over the isolation structure at a side of the transistor region, and an opposite second edge disposed over the first-type doped well. Two first ion doped wells are disposed in the transistor region and respectively at two sides of the transistor portion, and constitutes a transistor with the transistor portion. A second ion doped region is disposed in the capacitor region excluding the conductor and constitutes a capacitor with the capacitor portion.
摘要翻译：非易失性存储单元包括其中形成有隔离结构的半导体衬底，由此在其中限定晶体管区域和电容器区域。导体设置在隔离结构上，晶体管区域和布置在电容器区域中的第一类型掺杂阱。导体包括设置在第一型掺杂阱上的电容器部分，设置在晶体管区域上的晶体管部分，设置在晶体管区域侧的隔离结构上的第一边缘，型掺杂井。两个第一离子掺杂阱设置在晶体管区域中并分别设置在晶体管部分的两侧，并且构成具有晶体管部分的晶体管。第二离子掺杂区域设置在不包括导体的电容器区域中，并且与电容器部分构成电容器。

2. 发明授权

US08362535B2 Layout structure of non-volatile memory device 有权
标题翻译：非易失性存储器件的布局结构
公开(公告)号：US08362535B2
公开(公告)日：2013-01-29
申请号：US12568953
申请日：2009-09-29
申请人： Hung-Lin Shih , Jr-Bin Chen , Pei-Ching Yin , Hui-Fang Tsai
发明人： Hung-Lin Shih , Jr-Bin Chen , Pei-Ching Yin , Hui-Fang Tsai
IPC分类号： H01L27/108 , H01L29/66
CPC分类号： H01L27/0207 , H01L27/11519 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory cell includes a semiconductor substrate with isolation structures formed therein and thereby transistor region and capacitor region are defined therein. A conductor is disposed over the isolation structures, the transistor region and a first-type doped well disposed in the capacitor region. The conductor includes a capacitor portion disposed over the first-type doped well, a transistor portion disposed over the transistor region, a first edge disposed over the isolation structure at a side of the transistor region, and an opposite second edge disposed over the first-type doped well. Two first ion doped wells are disposed in the transistor region and respectively at two sides of the transistor portion, and constitutes a transistor with the transistor portion. A second ion doped region is disposed in the capacitor region excluding the conductor and constitutes a capacitor with the capacitor portion.
摘要翻译：非易失性存储单元包括其中形成有隔离结构的半导体衬底，由此在其中限定晶体管区域和电容器区域。导体设置在隔离结构上，晶体管区域和布置在电容器区域中的第一类型掺杂阱。导体包括设置在第一型掺杂阱上的电容器部分，设置在晶体管区域上的晶体管部分，设置在晶体管区域侧的隔离结构上的第一边缘，型掺杂井。两个第一离子掺杂阱设置在晶体管区域中并分别设置在晶体管部分的两侧，并且构成具有晶体管部分的晶体管。第二离子掺杂区域设置在不包括导体的电容器区域中，并且与电容器部分构成电容器。

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