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    • 1. 发明授权
    • Voltage-reducing device with low power dissipation
    • 具有低功耗的降压装置
    • US6014018A
    • 2000-01-11
    • US177205
    • 1998-10-22
    • Te-Sun WuHui-Fang TsaiTsun-Zu Lin
    • Te-Sun WuHui-Fang TsaiTsun-Zu Lin
    • G05F3/24G05F1/40
    • G05F3/242
    • A voltage-reducing device of low power dissipation is provided, including a plurality of transistors, which are self-connected as diode equivalent. These transistors are then cascaded in series in the same direction and coupled to a voltage source. Since every transistor has a threshold voltage, the voltage at the end of the forward-biased cascaded transistors will be lowered than the voltage source so as to provide a reduced voltage source. Furthermore, since the voltage adjustment of the device is based on the threshold voltage, there is hardly any power dissipation. In addition, we can use different threshold voltages from various transistors to provide different combinations of these threshold voltages to obtain the desired voltage drop.
    • 提供低功耗的降压装置,包括多个晶体管,它们作为二极管等效自连接。 然后将这些晶体管以相同的方向串联级联并耦合到电压源。 由于每个晶体管都具有阈值电压,所以正向偏置级联晶体管末端的电压将比电压源降低,从而提供一个降低的电压源。 此外,由于器件的电压调整基于阈值电压,因此几乎不存在功率消耗。 此外,我们可以使用不同晶体管的不同阈值电压来提供这些阈值电压的不同组合,以获得所需的电压降。
    • 4. 发明申请
    • Non-Volatile Memory Cell and Layout Structure of Non-Volatile Memory Device
    • 非易失性存储器单元和非易失性存储器件的布局结构
    • US20110073924A1
    • 2011-03-31
    • US12568953
    • 2009-09-29
    • Hung-Lin SHIHBin Chen, JR.Pei-Ching YinHui-Fang Tsai
    • Hung-Lin SHIHBin Chen, JR.Pei-Ching YinHui-Fang Tsai
    • H01L29/94
    • H01L27/0207H01L27/11519H01L27/11558H01L29/66825H01L29/7881
    • A non-volatile memory cell includes a semiconductor substrate with isolation structures formed therein and thereby transistor region and capacitor region are defined therein. A conductor is disposed over the isolation structures, the transistor region and a first-type doped well disposed in the capacitor region. The conductor includes a capacitor portion disposed over the first-type doped well, a transistor portion disposed over the transistor region, a first edge disposed over the isolation structure at a side of the transistor region, and an opposite second edge disposed over the first-type doped well. Two first ion doped wells are disposed in the transistor region and respectively at two sides of the transistor portion, and constitutes a transistor with the transistor portion. A second ion doped region is disposed in the capacitor region excluding the conductor and constitutes a capacitor with the capacitor portion.
    • 非易失性存储单元包括其中形成有隔离结构的半导体衬底,由此在其中限定晶体管区域和电容器区域。 导体设置在隔离结构上,晶体管区域和布置在电容器区域中的第一类型掺杂阱。 导体包括设置在第一型掺杂阱上的电容器部分,设置在晶体管区域上的晶体管部分,设置在晶体管区域侧的隔离结构上的第一边缘, 型掺杂井。 两个第一离子掺杂阱设置在晶体管区域中并分别设置在晶体管部分的两侧,并且构成具有晶体管部分的晶体管。 第二离子掺杂区域设置在不包括导体的电容器区域中,并且与电容器部分构成电容器。
    • 5. 发明授权
    • Layout structure of non-volatile memory device
    • 非易失性存储器件的布局结构
    • US08362535B2
    • 2013-01-29
    • US12568953
    • 2009-09-29
    • Hung-Lin ShihJr-Bin ChenPei-Ching YinHui-Fang Tsai
    • Hung-Lin ShihJr-Bin ChenPei-Ching YinHui-Fang Tsai
    • H01L27/108H01L29/66
    • H01L27/0207H01L27/11519H01L27/11558H01L29/66825H01L29/7881
    • A non-volatile memory cell includes a semiconductor substrate with isolation structures formed therein and thereby transistor region and capacitor region are defined therein. A conductor is disposed over the isolation structures, the transistor region and a first-type doped well disposed in the capacitor region. The conductor includes a capacitor portion disposed over the first-type doped well, a transistor portion disposed over the transistor region, a first edge disposed over the isolation structure at a side of the transistor region, and an opposite second edge disposed over the first-type doped well. Two first ion doped wells are disposed in the transistor region and respectively at two sides of the transistor portion, and constitutes a transistor with the transistor portion. A second ion doped region is disposed in the capacitor region excluding the conductor and constitutes a capacitor with the capacitor portion.
    • 非易失性存储单元包括其中形成有隔离结构的半导体衬底,由此在其中限定晶体管区域和电容器区域。 导体设置在隔离结构上,晶体管区域和布置在电容器区域中的第一类型掺杂阱。 导体包括设置在第一型掺杂阱上的电容器部分,设置在晶体管区域上的晶体管部分,设置在晶体管区域侧的隔离结构上的第一边缘, 型掺杂井。 两个第一离子掺杂阱设置在晶体管区域中并分别设置在晶体管部分的两侧,并且构成具有晶体管部分的晶体管。 第二离子掺杂区域设置在不包括导体的电容器区域中,并且与电容器部分构成电容器。
    • 7. 发明授权
    • Voltage supply controller
    • 电源控制器
    • US06420859B1
    • 2002-07-16
    • US09796950
    • 2001-02-27
    • Hui Fang TsaiChin Shin YehTe Sun Wu
    • Hui Fang TsaiChin Shin YehTe Sun Wu
    • G05F140
    • G05F3/242
    • A voltage supply control apparatus, suitable for being applied to a low voltage operation device. The voltage supply control apparatus has a high threshold voltage transistor and a low threshold voltage transistor. When the low voltage operation device is not working, the low threshold voltage transistor is cut off, and the voltage drop of a high voltage received from the power source terminal of the low voltage operation device is controlled by the high threshold voltage transistor. In contrast, when the low voltage operation device is working, the operation enable signal output thereby conducts the low threshold voltage transistor to control the voltage drop of the high voltage received from the power source terminal, so that a high potential is obtained.
    • 一种电压供给控制装置,适用于低压运转装置。 电压供给控制装置具有高阈值电压晶体管和低阈值电压晶体管。 当低电压操作装置不工作时,低阈值电压晶体管被切断,并且从低电压操作装置的电源端子接收的高电压的电压降由高阈值电压晶体管控制。 相反,当低电压操作装置工作时,由此操作使能信号输出导通低阈值电压晶体管,以控制从电源端子接收的高电压的电压降,从而获得高电位。