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1. 发明申请

US20150002322A1 SWITCHING SCHEME FOR ISI MITIGATION IN DATA CONVERTERS 审中-公开
标题翻译：数据转换器中ISI缓解的切换方案
公开(公告)号：US20150002322A1
公开(公告)日：2015-01-01
申请号：US14486918
申请日：2014-09-15
申请人： Abhishek Bandyopadhyay , Paul A. Baginski
发明人： Abhishek Bandyopadhyay , Paul A. Baginski
IPC分类号： H03M1/06 , H03K17/06 , H03M1/00 , H03M1/66
CPC分类号： H03M1/0617 , H03K17/063 , H03K17/162 , H03M1/002 , H03M1/0863 , H03M1/664 , H03M1/747
摘要： Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.
摘要翻译：本公开的实施例可以提供具有ISI减轻的三级单元元件的切换方案。三电平单元可以包括第一和第二电流源以及被布置成在第一和第二电流源之间形成三个电路分支的多个开关。第一电路支路可以包括在第一电流源和第一输出端之间并联连接的两个开关，以及并联连接在第二电流源和第一输出端之间的两个开关。第二电路支路可以包括并联连接在第一电流源和第二输出端之间的两个开关以及在第二电流源和第二输出端之间并联连接的两个开关。第三电路分支可以包括将第一电流源和第二电流源耦合到转储节点的开关。

2. 发明授权

US08847807B2 Switching scheme for ISI mitigation in data converters 有权
标题翻译：数据转换器中ISI缓解的切换方案
公开(公告)号：US08847807B2
公开(公告)日：2014-09-30
申请号：US13790472
申请日：2013-03-08
申请人： Abhishek Bandyopadhyay , Paul A. Baginski
发明人： Abhishek Bandyopadhyay , Paul A. Baginski
IPC分类号： H03M1/66 , H03K17/06
CPC分类号： H03M1/0617 , H03K17/063 , H03K17/162 , H03M1/002 , H03M1/0863 , H03M1/664 , H03M1/747
摘要： Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.
摘要翻译：本公开的实施例可以提供具有ISI减轻的三级单元元件的切换方案。三电平单元可以包括第一和第二电流源以及被布置成在第一和第二电流源之间形成三个电路分支的多个开关。第一电路支路可以包括在第一电流源和第一输出端之间并联连接的两个开关，以及并联连接在第二电流源和第一输出端之间的两个开关。第二电路支路可以包括并联连接在第一电流源和第二输出端之间的两个开关以及在第二电流源和第二输出端之间并联连接的两个开关。第三电路分支可以包括将第一电流源和第二电流源耦合到转储节点的开关。

3. 发明授权

US07423573B2 Architecture combining a continuous-time stage with a switched-capacitor stage for digital-to-analog converters and low-pass filters 有权
标题翻译：将连续时段与开关电容器级相结合，用于数模转换器和低通滤波器
公开(公告)号：US07423573B2
公开(公告)日：2008-09-09
申请号：US11616468
申请日：2006-12-27
申请人： Paul A. Baginski , Robert Adams , Khiem Nguyen
发明人： Paul A. Baginski , Robert Adams , Khiem Nguyen
IPC分类号： H03M1/66
CPC分类号： H03M3/502 , H03H19/004
摘要： A digital to analog converter (DAC) includes a first continuous-time stage that receives an input signal associated with a digital signal and performs continuous-time digital-to-analog conversion operations on the input signal. The first continuous-time stage outputs a first output signal. A second switched-capacitor stage receives the first output signal and performs switched-capacitor filtering of the first output signal. The second switched-capacitor stage outputs a second output signal that is sent to a low pass filter to form a continuous analog signal associated with the digital signal.
摘要翻译：数模转换器（DAC）包括第一连续时段，其接收与数字信号相关联的输入信号，并对输入信号执行连续时间数模转换操作。第一连续时段输出第一输出信号。第二开关电容器级接收第一输出信号并执行第一输出信号的开关电容滤波。第二开关电容器级输出发送到低通滤波器的第二输出信号以形成与数字信号相关联的连续模拟信号。

4. 发明授权

US09124283B2 Switching scheme for ISI mitigation in data converters 有权
标题翻译：数据转换器中ISI缓解的切换方案
公开(公告)号：US09124283B2
公开(公告)日：2015-09-01
申请号：US14486918
申请日：2014-09-15
申请人： Abhishek Bandyopadhyay , Paul A. Baginski
发明人： Abhishek Bandyopadhyay , Paul A. Baginski
IPC分类号： H03M1/66 , H03K17/06 , H03M1/06 , H03K17/16 , H03M1/00 , H03M1/08 , H03M1/74
CPC分类号： H03M1/0617 , H03K17/063 , H03K17/162 , H03M1/002 , H03M1/0863 , H03M1/664 , H03M1/747
摘要： Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.
摘要翻译：本公开的实施例可以提供具有ISI减轻的三级单元元件的切换方案。三电平单元可以包括第一和第二电流源以及被布置成在第一和第二电流源之间形成三个电路分支的多个开关。第一电路支路可以包括在第一电流源和第一输出端之间并联连接的两个开关，以及并联连接在第二电流源和第一输出端之间的两个开关。第二电路支路可以包括并联连接在第一电流源和第二输出端之间的两个开关以及在第二电流源和第二输出端之间并联连接的两个开关。第三电路分支可以包括将第一电流源和第二电流源耦合到转储节点的开关。

5. 发明申请

US20140145867A1 SWITCHING SCHEME FOR ISI MITIGATION IN DATA CONVERTERS 有权
标题翻译：数据转换器中ISI缓解的切换方案
公开(公告)号：US20140145867A1
公开(公告)日：2014-05-29
申请号：US13790472
申请日：2013-03-08
申请人： Abhishek Bandyopadhyay , Paul A. Baginski
发明人： Abhishek Bandyopadhyay , Paul A. Baginski
IPC分类号： H03K17/06 , H03M1/66
CPC分类号： H03M1/0617 , H03K17/063 , H03K17/162 , H03M1/002 , H03M1/0863 , H03M1/664 , H03M1/747
摘要： Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.
摘要翻译：本公开的实施例可以提供具有ISI减轻的三级单元元件的切换方案。三电平单元可以包括第一和第二电流源以及被布置成在第一和第二电流源之间形成三个电路分支的多个开关。第一电路支路可以包括在第一电流源和第一输出端之间并联连接的两个开关，以及并联连接在第二电流源和第一输出端之间的两个开关。第二电路支路可以包括并联连接在第一电流源和第二输出端之间的两个开关以及在第二电流源和第二输出端之间并联连接的两个开关。第三电路分支可以包括将第一电流源和第二电流源耦合到转储节点的开关。

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